Fibonacci p-code parallel adder

Claim 1

A Fibonacci p-code parallel adder comprising: an n-digit augend register and an n-digit addend register each having an original code write input to receive respectively an augend and an addend represented in Fibonacci p-codes, an ith bit position of said n bit positions of each of said registers comprising at least a flip-flop having a reset input, a complement output, a set input and a true output, said set inputs of said bit positions of said registers being used as said original code write inputs; a logic unit comprising n rewrite AND gates, an ith gate of said rewrite AND gates having three inputs and an output, first and second inputs of said ith rewrite AND gate being coupled respectively to said complement output of said ith bit position of said augend register and to said true output of said ith bit position of said addend register to provide for analyzing the condition of said flip-flops of said ith bit positions of said augend and addend registers; a delay unit comprising n delays, said output of said ith rewrite AND gate being coupled to said set input of said ith bit position of said augend register and to said reset input of said ith bit position of said addend register via a respective delay to transfer a 1 from said ith bit bit position of said addend register to said ith bit position, containing a 0, of said augend register; a Fibonacci p-code minimizing unit having two data inputs, a control input, and a normalize signal output, first and second data inputs of said Fibonacci p-code minimizing unit coupled respectively to said true outputs of said bit positions of said augend register and to said complement outputs of said bit positions of said addend register to provide for analyzing the codewords contained in said registers, said output of said Fibonacci p-code minimizing unit being coupled to a normalize signal input of said augend register to provide for the reduction, to the minimal form, of the codeword stored in said augend register and representing a sum code of the augend and addend; an end-of-addition detector having inputs coupled to said set outputs of said bit positions of said augend and addend registers, and having an output which produces an end-of-addition signal when the addend register contains a zero code and the augend register contains a sum code represented in the minimal form of a Fibonacci p-code; and a monitoring unit having inputs coupled to said true outputs of said bit positions of said augend and addend registers, and having an output which produces an error indicating signal when the form of the codeword contained in said augend register differs from the minimal form; wherein control inputs of said Fibonacci p-code minimizing unit and said logic unit are coupled to a control bus of the adder, and n is the length of the Fibonacci p-code and i=0,1,2 . . . , n-1.