Parallel digital beam-forming system

Claim 2

A parallel digital beam-former for use with an array of signal transducers comprising, in combination: a plurality of time-delay means, the number of said delay means being equal to the number of said transducers, each delay means being connected to receive as an input the output of a different one of said transducers and delaying said output in a series of increasing amounts; means connected to said delay means for causing said delay means to periodically and simultaneously sample the outputs of said transducers; means connected to said delay means for obtaining from each of said delay means a plurality of outputs comprising the series of increasingly delayed transducer signals, all outputs from a given delay means being simultaneously obtained, the series of outputs from any delay means being obtained at a different time than that from any other delay means, all delay means being tapped for their outputs before the next sampling of the outputs of the transducers; a plurality of serializing means connected to said time-delay means, each serializing means, having a plurality of inputs and providing a single output, the inputs to each serializing means being a set of delayed transducer signals, one input being derived from each transducer, the set of delayed transducer signals fed to each serializing means being chosen to conform to a different beam direction; and a plurality of means for transforming the output signals of said serializing means into signals indicative of beam signal strength, each transforming means being connected to a different one of said serializing means.

Claim 3

A parallel digital beam-former for use with an array of signal transducers comprising, in combination: a plurality of shift registers, each comprising a plurality of serially connected flip-flop stages and each register being connected to receive as an input the output of a different one of said transducers; means for simultaneously and periodically triggering all said shift registers, the output of its associated transducer being sampled by each shift register and the output of each flip-flop in any given shift register being forwarded as an input to the next flip-flop in the series at each triggering; a set of strobe gates, each being associated with a different one of said shift registers, each strobe gate consisting of a group of AND gates, each AND gate receiving as an input the output of a different flip-flop in the shift register associated with its strobe gate; means for actuating said strobe gates in consecutive order, all AND gates in a given strobe gate being actuated simultaneously to pass the output signals of the flip-flops to which the AND gates are connected; a set of beam gates equal in number to the predetermined number of beams which are to be formed, each beam gate consisting of a group of OR gates, each OR gate in a given beam gate being connected to a different AND gate and to no more than one AND gate in any given shift register, the set of AND gates which are connected to the OR gates of any given beam gate being selected to provide the delays required for the desired beam direction for that beam gate; and a set of binary counters, each connected to a different one of said beam gates, the output of each binary counter being indicative of the signal strength in its selected beam direction.

Claim 4

A parallel digital beam-former for use with an array of signal transducers comprising, in combination: a plurality of shift registers, each comprising a plurality of serially connected flip-flop stages and each register being connected to receive as an input the output of a different one of said transducers; means for simultaneously and periodically triggering all said shift registers, the output of its associated transducer being sampled by each shift register and the output of each flip-flop in any given shift register being forwarded as an input to the next flip-flop in the series at each triggering; a set of strobe gates, each being associated with a different one of said shift registers, each strobe gate consisting of a group of AND gates, each AND gate receiving as an input the output of a different flip-flop in the shift register associated with its strobe gate; means for actuating said strobe gates in consecutive order, all AND gates in a given strobe gate being actuated simultaneously to pass the output signals of the flip-flops to which the AND gates are connected; a set of beam gates equal in number to the predetermined number of beams which are to be formed, each beam gate consisting of a group of OR gates, each OR gate in a given beam gate being connected to a different AND gate and to no more than one AND gate in any given shift register, the set of AND gates which are connected to the OR gates of any given beam gate being selected to provide the delays required for the desired beam direction for that beam gate; and a set of binary counters, each connected to a different one of said beam gates, the output of each binary counter being indicative of the signal strength in its selected beam direction.