US4270125A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Display system
Assignee: General Electric Co
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Filing: 1976-09-13
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Granted: 1981-05-26
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Expires: 1996-09-13
Abstract
Abstract System for displaying computer generated information on a display screen such as a standard television raster by mapping memory bits onto corresponding points of the raster. The information is applied serially to the television circuits in synchronization with the sweep rate of the television. Horizontal and vertical synchronization signals are also generated to control the receiver sweep circuits.
Inventors
- 👤 Joseph A. Weisbecker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:43
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/18
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
242 words
A system for displaying a pattern on a raster scanned display device by mapping bits from a display location in a memory associated with a computer onto the raster as contrasting spots depending on the value of each bit, wherein said computer is responsive to a direct memory access request to produce on a data bus, data signals retrieved from said memory at a location specified by a pointer address register, comprising the combination of: clock means for producing timing signals; output means for coupling signals to said display device; means, including interval timing means, responsive to said timing signals, for producing horizontal synchronizing signals and applying them to said output means; line counter means responsive to said horizontal synchronizing signals for producing output signals identifying individual horizontal lines; first decoder means responsive to said interval timing means and to said line counter means for supplying direct memory access requests to said computer; second decoder means responsive to said line counter means for supplying vertical synchronization signals to said output means; means for storing data signals from said data bus in response to a signal derived from said timing signals when said computer responds to a direct memory access request and for shifting said data serially to said output means in response to said timing signals; and a plurality of gating means, responsive to a command signal, for coupling the output signals from the line counter means to the data bus means.
Claim 2
Independent Claim
242 words
A system for displaying a pattern on a raster scanned display device by mapping bits from a display location in a memory associated with a computer onto the raster as contrasting spots depending on the value of each bit, wherein said computer is responsive to a direct memory access request to produce on a data bus, data signals retrieved from said memory at a location specified by a pointer address register, comprising the combination of: clock means for producing timing signals; output means for coupling signals to said display device; means, including interval timing means, responsive to said timing signals, for producing horizontal synchronizing signals and applying them to said output means; line counter means responsive to said horizontal synchronizing signals for producing output signals identifying individual horizontal lines; first decoder means responsive to said interval timing means and to said line counter means for supplying direct memory access requests to said computer; second decoder means responsive to said line counter means for supplying vertical synchronization signals to said output means; means for storing data signals from said data bus in response to a signal derived from said timing signals when said computer responds to a direct memory access request and for shifting said data serially to said output means in response to said timing signals; and a plurality of gating means, responsive to a command signal, for coupling the output signals from the line counter means to the data bus means.
Claim 3
Independent Claim
246 words
A system for displaying a pattern on a raster scanned display device by mapping bits from a display location in a memory associated with a computer onto the raster as contrasting spots depending on the value of each bit, wherein said computer is responsive to a direct memory access request to produce on a data bus, data signals retrieved from said memory at a location specified by a pointer address register, comprising the combination of: clock means for producing timing signals; output means for coupling signals to said display device; means, including interval timing means, responsive to said timing signals, for producing horizontal synchronizing signals and applying them to said output means; line counter means responsive to said horizontal synchronizing signals for producing output signals identifying individual horizontal lines; first decoder means responsive to said interval timing means and to said line counter means for supplying direct memory access requests to said computer; second decoder means responsive to said line counter means for supplying vertical synchronization signals to said output means; and means for storing data signals from said data bus in response to a signal derived from said timing signals when said computer responds to a direct memory access request and for shifting said data serially to said output means in response to said timing signals; said output means including an Exclusive-OR gate receptive of said vertical and horizontal synchronizing signals for producing a composite synchronizing signal having horizontal serrations in said vertical synchronization signal.
Claim 4
Independent Claim
246 words
A system for displaying a pattern on a raster scanned display device by mapping bits from a display location in a memory associated with a computer onto the raster as contrasting spots depending on the value of each bit, wherein said computer is responsive to a direct memory access request to produce on a data bus, data signals retrieved from said memory at a location specified by a pointer address register, comprising the combination of: clock means for producing timing signals; output means for coupling signals to said display device; means, including interval timing means, responsive to said timing signals, for producing horizontal synchronizing signals and applying them to said output means; line counter means responsive to said horizontal synchronizing signals for producing output signals identifying individual horizontal lines; first decoder means responsive to said interval timing means and to said line counter means for supplying direct memory access requests to said computer; second decoder means responsive to said line counter means for supplying vertical synchronization signals to said output means; and means for storing data signals from said data bus in response to a signal derived from said timing signals when said computer responds to a direct memory access request and for shifting said data serially to said output means in response to said timing signals; said output means including an Exclusive-OR gate receptive of said vertical and horizontal synchronizing signals for producing a composite synchronizing signal having horizontal serrations in said vertical synchronization signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-25 | 1984-11-24 | 1985-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-25 | 1988-11-24 | 1989-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-25 | 1992-11-24 | 1993-05-26 | $7700.00 | Window Closed / Lapsed |