US4267634A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making a chip circuit component
Assignee: American Components Inc
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Filing: 1978-04-05
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Granted: 1981-05-19
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Expires: 1998-04-05
Abstract
Abstract The present method and device provides that a thickness of wet ceramic material is laid down and partially dried to provide a base. This step is followed by screen printing one or more patterns of electrical resistance material on the upper surface of the partially dried ceramic base. Thereafter a second thickness of said wet ceramic is laid down and partially dried. In the event that the fabricator desires to provide a plurality of resistance paths, or a capacitor, in a single package, the foregoing process can be repeated with additional patterns of resistance material laid down or conductor material for a capacitor laid down, on the upper layer of partially dried ceramic material. The resistance or conductor patterns are sandwiched by additional thicknesses of ceramic materials screen stacked thereon. When the desired package has been achieved, the multi layered arrangement is given a final drying and it is then diced and fired. Thereafter termination means are provided to the fired diced sections, thus making up chip components.
Inventors
- 👤 Charles L. Wellard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:51
CPC Classifications
H; H01; H01C; H01C17/00; H01C17/006; H01C17/06; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082; Y10T29/49099; Y10T29/49101
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
221 words
A method for making a chip circuit component comprising the steps of: depositing individually a first plurality of thin layers of wet ceramic material in a stacked form on a sheet means and partially drying each of said thin layers of ceramic between each layer deposition thereof; depositing a pattern of electrical resistance material in a wet form onto the uppermost, partially dried, ceramic layer in said stack and partially drying said electrical resistance material; depositing individually a second plurality of thin layers of wet ceramic material in a stacked form onto the partially dried electrical resistance material and partially drying each of said thin layers of ceramic between each layer deposition thereof; further drying the above described stack consisting of the partially dried first plurality of ceramic layers, the partially dried electrical resistance material and the partially dried second plurality of ceramic layers; cutting the further dried, above described, stack into a plurality of chips each of which has a section of said electrical resistance material and abutting two edges thereof surrounded by dried ceramic material, firing said plurality of chips until the ceramic material is hardened into a solid ceramic housing; and securing terminal means to said two edges of the ceramic material and forming said terminal means integral with the resistance material disposed in said solid ceramic housing.
Claim 2
Independent Claim
221 words
A method for making a chip circuit component comprising the steps of: depositing individually a first plurality of thin layers of wet ceramic material in a stacked form on a sheet means and partially drying each of said thin layers of ceramic between each layer deposition thereof; depositing a pattern of electrical resistance material in a wet form onto the uppermost, partially dried, ceramic layer in said stack and partially drying said electrical resistance material; depositing individually a second plurality of thin layers of wet ceramic material in a stacked form onto the partially dried electrical resistance material and partially drying each of said thin layers of ceramic between each layer deposition thereof; further drying the above described stack consisting of the partially dried first plurality of ceramic layers, the partially dried electrical resistance material and the partially dried second plurality of ceramic layers; cutting the further dried, above described, stack into a plurality of chips each of which has a section of said electrical resistance material and abutting two edges thereof surrounded by dried ceramic material, firing said plurality of chips until the ceramic material is hardened into a solid ceramic housing; and securing terminal means to said two edges of the ceramic material and forming said terminal means integral with the resistance material disposed in said solid ceramic housing.
Claim 3
Dependent Claim
304 words
A method for making a chip circuit according to claim 1 wherein there is further included prior to said further drying step, the steps of: depositing a first pattern of electrical conducting material in a wet form onto the uppermost surface of said partially dried ceramic layer of said second plurality of ceramic layers and partially drying said first pattern of electrical conducting material, depositing individually a third pluraity of thin layers of wet ceramic material in a stacked form onto the partially dried first pattern of electrical conducting material and partially drying each of said thin layers of ceramic between each layer deposition thereof; depositing a second pattern of electrical conducting material in a wet form onto the surface of the uppermost of said partially dried ceramic layers of said third plurality of ceramic layers and partially drying said second pattern of electrical conducting material; depositing individually a fourth plurality of thin layers of wet ceramic material in a stacked form onto the partially dried second pattern of electrically conducting material and partially drying each of said thin layers of ceramic material between each layer deposition thereof; said further drying steps including further drying of the above described stack consisting of the partially dried first plurality of ceramic layers, the partially dried electrical resistance material, the partially dried second plurality of ceramic layers, the partially dried first pattern of electrical conducting material, the partially dried third plurality of ceramic layers, the partially dried second pattern of electrical conducting material and the partially dried fourth plurality of ceramic layers; said cutting step including cutting the further dried, above described, stack so that each of said plurality of chips has a section of said electrical resistance material and each has sections of each of said first and second electrical conducting material abutting two edges thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-18 | 1984-11-17 | 1985-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-18 | 1988-11-17 | 1989-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-18 | 1992-11-17 | 1993-05-19 | $7700.00 | Window Closed / Lapsed |