Method to make an integrated circuit with severable conductive strip

Claim 1

Method to make an integrated circuit by planar technology having a metallic strip (1) adapted to be severed at a predetermined location (9) on the surface area of the chip by application of electrical current to said strip. comprising the steps of providing a silicon substrate chip (3, 4, 5); forming a zone of lesser heat dissipation capacity than surrounding areas at said predetermined location beneath the metallic strip to provide a burn-out point at said predetermined location including forming a layer (11) of silicon oxide on said substrate chip of increased thickness with respect to surrounding areas at said predetermined location by utilizing a masking pattern having two windows adjacent said predetermined location (9) while leaving a bridge at said location between said two windows, and diffusing doping material into said chip into the zones of said windows to form diffusion zones (8a, 8b) in said chip adjacent to and beneath said predetermined location (9) and forming a covering silicon oxide layer (11) at said diffusion zones (8a, 8b) and over said bridge of silicon oxide whereby the silicon oxide bridge will have a thickened portion (10) with respect to the adjacent areas of the silicon oxide layer (11); and applying a metallic conductive layer (1) in strip form over the silicon oxide layer located over said diffusion zones (8a, 8b) and over said thickened portion (10), to provide said zone of lesser heat dissipation capacity at said location (9) than the heat dissipation capacity of the oxide layer (11) in areas surrounding said predetermined location.