US4267594A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Decommutator patchboard verifier
Assignee: National Aeronautics and Space Administration
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Filing: 1979-06-22
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Granted: 1981-05-12
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Expires: 1999-06-22
Abstract
Abstract A system for automatically verifying the connections between terminals of a patchboard. The system includes a back plane having a plurality of plugs provided therein corresponding to the pins of the patchboard so that the patchboard can be plugged therein. A plurality of decoders are connected to the plugs of the back plane so that a signal can be sequentially applied to each plug of the back plane under control of a stepping register and a control circuit. A plurality of data selectors are also connected to the plugs of the back plane and under control of a second external register and said control circuit sequentially make connections between an output circuit and the plugs of the back plane so as to patch the signal applied to a respective plug through a patch connection to the output circuit. By making the above connections in a controlled manner, the precise locations of the patches on the patchboard can be identified and compared with previously stored information in a memory unit.
Inventors
- 👤 John W. Brunson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:19
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2832; G01R31/2834; G01R31/50; G01R31/66; G01R31/67
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
342 words
A system for verifying the connections between terminals of a patchboard comprising: (a) a back plane; (b) a plurality of plugs provided in said back plane corresponding in number and position to said terminals of said patchboard so that said patchboard that is to be verified can be plugged therein; (c) a plurality of decoders connected to said plugs of said back plane; (d) a control circuit means; (e) memory means connected to said control circuit means, means for storing information in said memory means representing the correct patching program of said patchboard which is being verified; (f) first stepping register means connected between said control circuit means and said plurality of decoders for selectively supplying signals through said decoders to said plugs of said back plane under control of said control circuit means; (g) a plurality of data selector means connected to said plugs of said back plane; (h) an output circuit; (i) second stepping register means connected between said control circuit means and said plurality of data selector means for selectively making connection between said plugs through said data selector means to said output circuit causing a signal to be produced at said output circuit identifying the connections between the terminals of said patchboard, (j) comparator means connected to said memory means and output circuit for comparing signals produced at said output circuit with said information in said memory for verifying said connections between terminals of said patchboard; and (k) said plurality of decoders including: (i) first, second and third level decoders; (ii) each of said decoders having input and output terminals; (iii) means for connecting predetermined input terminals of said decoders to said first stepping register means; (iv) means for connecting said output terminals of said first level decoders to predetermined input terminals of said second level decoders; (v) means for connecting said output terminals of said second level decoders to predetermined input terminals of said third level decoders; and (vi) means for connecting said output terminals of said third level decoders to predetermined plugs of said back frame.
Claim 2
Independent Claim
342 words
A system for verifying the connections between terminals of a patchboard comprising: (a) a back plane; (b) a plurality of plugs provided in said back plane corresponding in number and position to said terminals of said patchboard so that said patchboard that is to be verified can be plugged therein; (c) a plurality of decoders connected to said plugs of said back plane; (d) a control circuit means; (e) memory means connected to said control circuit means, means for storing information in said memory means representing the correct patching program of said patchboard which is being verified; (f) first stepping register means connected between said control circuit means and said plurality of decoders for selectively supplying signals through said decoders to said plugs of said back plane under control of said control circuit means; (g) a plurality of data selector means connected to said plugs of said back plane; (h) an output circuit; (i) second stepping register means connected between said control circuit means and said plurality of data selector means for selectively making connection between said plugs through said data selector means to said output circuit causing a signal to be produced at said output circuit identifying the connections between the terminals of said patchboard, (j) comparator means connected to said memory means and output circuit for comparing signals produced at said output circuit with said information in said memory for verifying said connections between terminals of said patchboard; and (k) said plurality of decoders including: (i) first, second and third level decoders; (ii) each of said decoders having input and output terminals; (iii) means for connecting predetermined input terminals of said decoders to said first stepping register means; (iv) means for connecting said output terminals of said first level decoders to predetermined input terminals of said second level decoders; (v) means for connecting said output terminals of said second level decoders to predetermined input terminals of said third level decoders; and (vi) means for connecting said output terminals of said third level decoders to predetermined plugs of said back frame.
Claim 3
Dependent Claim
157 words
The system as set forth in claim 1 wherein said first stepping register means comprises: (a) a first multi-bit sequential stepping register having an input terminal and a plurality of output terminals representing bits of information of different significance; (b) means for connecting said input terminal of said first stepping register to said control circuit means for sequentially stepping said first stepping register responsive to receiving signals from said control circuit means; (c) means for connecting predetermined output terminals of said first stepping register representing least significant bits of information to predetermined input terminals of said third level decoders; (d) means for connecting predetermined output terminals of said first stepping register representing the next most significant bits of information to predetermined input terminals of said second level decoders, and (e) means for connecting predetermined output terminals of said first stepping register representing the most significant bits of information to predetermined input terminals of said first level decoders.
Claim 4
Dependent Claim
117 words
The system as set forth in claim 1 wherein said plurality of data selector means comprises: (a) first, second and third level data selectors; (b) each of said data selectors having input, output, and control terminals; (c) means for connecting predetermined control terminals of said data selectors to said second stepping register means; (d) means for connecting said output terminals of said first level data selectors to predetermined input terminals of said second level data selectors; (e) means for connecting said output terminals of said second level data selectors to predetermine input terminals of said third level data selectors; and (f) means for connecting said output terminal of said third level data selector to said output circuit.
Claim 5
Dependent Claim
158 words
The system as set forth in claim 3 wherein said second stepping register means comprises: (a) a second multi-bit sequential stepping register having an input terminal and a plurality of output terminals representing bits of information of different significance; (b) means for connecting said input terminal of said second stepping register to said control circuit means for sequentially stepping said stepping register responsive to receiving signals from said control circuit means, (c) means for connecting predetermined output terminals of said second stepping register representing least significant bits of information to predetermined input terminals of said first level data selectors, (d) means for connecting predetermined output terminals of said second stepping register representing the next most significant bits of information to predetermined input terminals of said second level data selectors; and (e) means for connecting predetermined output terminals of said second stepping register representing the most significant bits of information to predetermined input terminals of said third level decoders.
Claim 6
Dependent Claim
57 words
The system as set forth in claim 1 further comprising: (a) an output terminal provided on said comparator means for receiving signals indicating whether the information appearing on the output circuit matches the information stored in said memory means, (b) a printer connected to the output terminal of said comparator means for recording the information produced thereon.
Claim 7
Independent Claim
291 words
A system for verifying the connection between terminals of a patchboard comprising: (a) a back plane, (b) a plurality of plugs provided in said back plane corresponding in number and position to said terminals of said patchboard so that said patchboard that is to be verified can be plugged therein; (c) a plurality of decoders being connected to said plugs of said back plane; (d) a control circuit means; (e) memory means connected to said control circuit means; (f) means for storing information in said memory means representing the correct patching program of said patch board which is being verified; (g) first stepping register means connected between said control circuit means and said plurality of decoders for selectively supplying signals through said decoders to said plugs of said back plane under control of said control circuit means, (h) a plurality of data selector means connected to said plugs of said back plane; (i) an output circuit; (j) second stepping register means connected between said control circuit means and said plurality of data selector means for selectively making connection between said plugs through said data selector means to said output circuit causing a signal to be produced at said output circuit identifying said connections between said terminals of said patchboard; (k) said control circuit means synchronizing the stepping of said first stepping register with said second stepping register so that as a signal is sequentially supplied from said first stepping register to each plug of said back plane and while said signal is being supplied to a particular plug connection in sequentially made between said output circuit and every other plug of said back plane so as to determine if there is a patch between said particular plug and any other plug.
Claim 8
Independent Claim
291 words
A system for verifying the connection between terminals of a patchboard comprising: (a) a back plane, (b) a plurality of plugs provided in said back plane corresponding in number and position to said terminals of said patchboard so that said patchboard that is to be verified can be plugged therein; (c) a plurality of decoders being connected to said plugs of said back plane; (d) a control circuit means; (e) memory means connected to said control circuit means; (f) means for storing information in said memory means representing the correct patching program of said patch board which is being verified; (g) first stepping register means connected between said control circuit means and said plurality of decoders for selectively supplying signals through said decoders to said plugs of said back plane under control of said control circuit means, (h) a plurality of data selector means connected to said plugs of said back plane; (i) an output circuit; (j) second stepping register means connected between said control circuit means and said plurality of data selector means for selectively making connection between said plugs through said data selector means to said output circuit causing a signal to be produced at said output circuit identifying said connections between said terminals of said patchboard; (k) said control circuit means synchronizing the stepping of said first stepping register with said second stepping register so that as a signal is sequentially supplied from said first stepping register to each plug of said back plane and while said signal is being supplied to a particular plug connection in sequentially made between said output circuit and every other plug of said back plane so as to determine if there is a patch between said particular plug and any other plug.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-11 | 1984-11-10 | 1985-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-11 | 1988-11-10 | 1989-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-11 | 1992-11-10 | 1993-05-12 | $7700.00 | Window Closed / Lapsed |