Processor for a graphic terminal

Claim 1

A digital MOS processor connected on to a command unit and to a TV set enabling: in a writing mode, the data of a graphic image to be produced and stored in an external memory unit and, in a reading mode, these stored data to be read and displayed on the CRT screen of the TV set; characterised in that, on a single microchip of a semi-conductor substrate, it comprises: a two-way data bus comprising input/output means and terminals enabling it to be connected to the command unit; an address bus comprising means enabling it to be connected to the command unit; terminals carrying signals allowing dialogue with the command unit; a control unit which produces signals enabling the time bases of the TV set to be synchronized, address signals enabling the data stored in the memory unit to be read, signals for controlling the luminance levels of the CRT screen of the TV set and internal timing signals; this control unit being connected to an external clock circuit comprising a dot clock and a dividing counter which supplies addressing signals to the memory unit; a graphic unit comprising a symbol generator and a vector generator coupled to a writing pointer which supplies write address signals to the memory unit; a register connected to the data bus and to the address bus and enabling command words to be stored; a plurality of registers connected to the command bus and to the address bus and enabling data words to be stored; a first multiplexer connected to the control unit and to the graphic unit and enabling the reading and writing address signals of the memory unit to be multiplexed in dependence upon the mode of operation (reading or writing) of the processor; a second multiplexer connected to the first multiplexer and enabling the low part and the high part of the writing addresses and reading addresses to be multiplexed at the rate of the internal clock signal; a third multiplexer connected to the control unit and to the graphic unit and enabling certain of the reading and writing address signals to be connected according to the format of the TV image; a reading means connected to the control unit and enabling a dot of the graphic image displayed on the CRT screen of the TV set to be read; this reading means comprising a register connected to the data bus which enables the data of the address of the displayed dot to be stored, a means for forcing the graphic image to the "white" level, a means for reading the content of the register and a means for indicating the busy state of this reading means; an interruption element comprising a means for producing a word indicating the state of the graphic unit, a masking means controlled by masking bits contained in the control register, a means for recording the state word connected to the data bus and to the address bus and comprising means for reading this recording means, synchronizing means for synchronizing a means for decoding the command words stored in the command register, an erasing means enabling the data of the graphic image stored in the memory unit to be erased or a continuous background to be stored in the memory unit, the control unit comprising means enabling the format (interlaced frames or paired frames) of the TV image to be modified.