Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
75 words
A signal generator comprising: a shift register into which an input signal including a preset number of bits is coupled to produce a serial output signal at an output terminal thereof, a means for feeding another serial signal which is inverse to said serial output signal to an input terminal of a first stage of said shift register, and a pulse width modulation means for modulating a carrier with output signals from said output terminal.
Claim 2
Dependent Claim
75 words
A signal generator comprising: a shift register into which an input signal including a preset number of bits is coupled to produce a serial output signal at an output terminal thereof, a means for feeding another serial signal which is inverse to said serial output signal to an input terminal of a first stage of said shift register, and a pulse width modulation means for modulating a carrier with output signals from said output terminal.
Claim 3
Dependent Claim
94 words
A signal generator comprising: a shift register of parallel input serial output type into input terminals of which an input signal including a preset number of bits is to be put to produce a serial output signal at an output terminal thereof, a connection for feeding another serial signal which is of opposite polarity to said serial output signal to an input terminal of a first stage of said shift register, and an output pulse generator which generates output pulses of broader and narrower widths responding to the output signals of said shift register.
Claim 4
Dependent Claim
94 words
A signal generator comprising: a shift register of parallel input serial output type into input terminals of which an input signal including a preset number of bits is to be put to produce a serial output signal at an output terminal thereof, a connection for feeding another serial signal which is of opposite polarity to said serial output signal to an input terminal of a first stage of said shift register, and an output pulse generator which generates output pulses of broader and narrower widths responding to the output signals of said shift register.
Claim 5
Dependent Claim
178 words
A signal generator comprising: shift register means having plural stages and parallel inputs, one coupled to each stage thereof, for receiving a multi-bit parallel input signal having a predetermined number of bits corresponding to the number of stages of said shift register and for providing a serial output signal at a first output thereof and an inverted serial output signal at a second output thereof; means for coupling said inverted serial output signal to the first stage of said shift register; and pulse width modulation means for providing an output signal having a pulse width modulated bits responsive to the serial output signal of said shift register means, whereby the output signal of said pulse width modulator is a multi-bit serial signal of fixed length having first and second groups of pulses, each group containing a number of pulses equal to the number of stages of said shift register means and parallel input bits, each bit of the second group corresponding to a bit of the first group and having a pulse width that is inversely proportional thereto.
Claim 6
Dependent Claim
178 words
A signal generator comprising: shift register means having plural stages and parallel inputs, one coupled to each stage thereof, for receiving a multi-bit parallel input signal having a predetermined number of bits corresponding to the number of stages of said shift register and for providing a serial output signal at a first output thereof and an inverted serial output signal at a second output thereof; means for coupling said inverted serial output signal to the first stage of said shift register; and pulse width modulation means for providing an output signal having a pulse width modulated bits responsive to the serial output signal of said shift register means, whereby the output signal of said pulse width modulator is a multi-bit serial signal of fixed length having first and second groups of pulses, each group containing a number of pulses equal to the number of stages of said shift register means and parallel input bits, each bit of the second group corresponding to a bit of the first group and having a pulse width that is inversely proportional thereto.