Power converter control

Claim 2

A circuit for generating signals for rendering conductive the controlled rectifiers of a power conversion system to thereby control the power supplied to a load from a source of alternating current voltage comprising: (a) means to sense a designated point in the cycle of the source voltage and to supply an output signal in response thereto; (b) means responsive to said output signal to develop multiple bit address signals representing a timephase relationship with respect to said designated point; (c) a memory system having a plurality of selectively addressable, multiple bit storage locations to be addressed by said address signals, individual ones of said storage locations each containing predetermined data designating the firing sequence and time of firing the rectifiers of the power conversion system; and, (d) means responsive to the contents of the addressed locations to develop signals for the selective rendering conductive of individual ones of said rectifiers.

Claim 3

The invention in accordance with claim 1 wherein said means to develop said address signals develops a digital count.

Claim 4

The invention in accordance with claim 1 wherein said memory system is comprised of two distinct areas, the first of said areas containing data respecting the sequence of cell firing and the second of said areas containing values corresponding to a sinusoidal wave shape.

Claim 5

The invention in accordance with claim 3 wherein the address for said first area of memory is comprised of a portion of said address signals and a portion of the contents of the previously addressed location of said first area and the address for said second area of memory is comprised of a second portion of said address signals and a second portion of the contents of the last addressed location of the first area.

Claim 6

The invention in accordance with claim 4 further including means to develop an additional signal indicative of one of two types of converter operation, said additional signal being included within the address of said first area of memory.

Claim 7

The invention in accordance with claim 5 for application when the power conversion system supplies power to a motor load wherein said additional signal designates desired direction of motor torque.

Claim 8

The invention in accordance with claim 3 wherein said memory system comprises first and second read only memories as said first and second areas.

Claim 9

The invention in accordance with claim 1 further including means responsive to signals indicative of prescribed system operating conditions to alter the development of the signals for rendering the rectifiers conductive.

Claim 10

A firing circuit for the generation of firing signals operative to selectively render conductive the individual cells of a power converter supplying a d.c. load from a polyphase a.c. source comprising: (a) means to identify a prescribed relationship between two phase voltages of said source and to output a signal indicative thereof; (b) synthesizing means responsive to said signal for developing a multiple bit digital count representing a phase displacement with respect to said prescribed relationship; (c) a memory system including a plurality of selectively addressable, multiple bit storage locations to be addressed by said digital count, said storage locations each retaining predetermined data defining the angle and sequence of rendering the cells of the converter conductive; and, (d) means responsive to the contents of sequentially addressed storage locations to generate the signals for rendering the cells conductive.

Claim 11

A firing circuit for the generation of firing signals operative to selectively render conductive the individual cells of a power converter supplying a d.c. load from a polyphase a.c. source comprising: (a) means to identify a prescribed relationship between two phase voltages of said source and to output a signal indicative thereof; (b) synthesizing means responsive to said signal for developing a multiple bit digital count representing a phase displacement with respect to said prescribed relationship; (c) a memory system including a plurality of selectively addressable, multiple bit storage locations to be addressed by said digital count, said storage locations each retaining predetermined data defining the angle and sequence of rendering the cells of the converter conductive; and, (d) means responsive to the contents of sequentially addressed storage locations to generate the signals for rendering the cells conductive.

Claim 12

The invention in accordance with claim 9 wherein said synthesizing means includes means to generate a series of pulses at a rate which is a multiple of the frequency of the a.c. source and a digital counter response to said pulses for developing said count.

Claim 13

The invention in accordance with claim 9 wherein said memory system is comprised of two distinct areas, the first of said areas containing data respecting the sequence of cell firing and the second of said areas containing values corresponding to a sinusoidal wave shape.

Claim 14

The invention in accordance with claim 11 wherein the address for said first area of memory is comprised of a portion of said count and a portion of the contents of the previously addressed location of said first area and the address for said second area of memory is comprised of a second portion of said count and a second portion of the contents of the last addressed location of the first area.

Claim 15

The invention in accordance with claim 12 further including means to develop an additional signal indicative of one of two types of converter operation, said additional signal being included within the address of said first area of memory.

Claim 16

The invention in accordance with claim 13 for application when the power conversion system supplies power to a motor load wherein said additional signal designates desired direction of motor torque.

Claim 17

The invention in accordance with claim 11 wherein said memory system comprises first and second read only memories as said first and second areas.

Claim 18

A circuit for generating firing pulses for rendering conductive the thyristors of a power conversion system at a specified time with respect to an alternating current input signal comprising: (a) means to sense a designated point in the cycle of the input signal and to provide an output signal in response thereto; (b) means responsive to said output signal to develop a digital count representing a timephase relationship with respect to said designated point; (c) first memory means having a plurality of selectively addressable storage locations the individual contents of which designate the next cell of the converter to be fired and a desired shift angle of thyristor firings, said first memory means being addressed in response to address signals applied thereto, a first portion of said address signals comprised of a selected part of said digital count and a second portion derived from a latch means; (d) latch means for providing said second portion in response to selected input signals including a portion of the contents of the last addressed location of said first memory means designating the next cell to be fired, a signal designating cell firing sequence and a firing control signal indicative of a proper time for firing a cell; (e) a second memory means having a plurality of selectively addressable storage locations the individual contents of which represent individual points of a sinusoid wave shape, said second memory means receiving address signals comprised of a second portion of said digital count and an output of the first memory means resulting from the then being addressed location and designating a shifted angle for the next to be fired thyristor; (f) a digital-to-analog converter responsive to the contents of sequentially addressed locations of said second memory means to develop an output signal representing at least a segment of a sinusoidal wave; (g) means to generate a reference signal indicative of a desired output of the converter; (h) comparator means responsive to said reference signal and the contents of the then being addressed location of said second memory means to develop an output signal indicative of the time to fire a cell in said converter; and, (i) further means within said logic means responsive to the output of said comparator means to outut a signal to effect the firing of converter cells.

Claim 19

A circuit for generating firing pulses for rendering conductive the thyristors of a power conversion system at a specified time with respect to an alternating current input signal comprising: (a) means to sense a designated point in the cycle of the input signal and to provide an output signal in response thereto; (b) means responsive to said output signal to develop a digital count representing a timephase relationship with respect to said designated point; (c) first memory means having a plurality of selectively addressable storage locations the individual contents of which designate the next cell of the converter to be fired and a desired shift angle of thyristor firings, said first memory means being addressed in response to address signals applied thereto, a first portion of said address signals comprised of a selected part of said digital count and a second portion derived from a latch means; (d) latch means for providing said second portion in response to selected input signals including a portion of the contents of the last addressed location of said first memory means designating the next cell to be fired, a signal designating cell firing sequence and a firing control signal indicative of a proper time for firing a cell; (e) a second memory means having a plurality of selectively addressable storage locations the individual contents of which represent individual points of a sinusoid wave shape, said second memory means receiving address signals comprised of a second portion of said digital count and an output of the first memory means resulting from the then being addressed location and designating a shifted angle for the next to be fired thyristor; (f) a digital-to-analog converter responsive to the contents of sequentially addressed locations of said second memory means to develop an output signal representing at least a segment of a sinusoidal wave; (g) means to generate a reference signal indicative of a desired output of the converter; (h) comparator means responsive to said reference signal and the contents of the then being addressed location of said second memory means to develop an output signal indicative of the time to fire a cell in said converter; and, (i) further means within said logic means responsive to the output of said comparator means to outut a signal to effect the firing of converter cells.