Clocking system for MOS transistor logic circuit

Claim 1

A modular integrated circuit including a plurality of complementary MOS transistor switching circuits for performing a variety of logic functions comprising: clock means for driving said switching circuits over a cycle including four consecutive time periods T 1 to T 4 , said clock means including a first clock pulse train having a logic one in period T 1 and a logic zero in periods T 2 , T 3 , T 4 , a second clock pulse train having a logic one in period T 3 and a logic zero in periods T 1 , T 2 , T 4 and a third clock pulse train having a logic one in periods T 3 and T 4 and a logic zero in periods T 1 and T 2 , respectively, each of said clock pulse trains being periodic whereby each of said four consecutive time periods are successively reproduced in periodic form; a type I circuit means responsive to said first clock pulse train, said type I circuit means including a complementary MOS inverter circuit coupled between the drain of a first N-channel MOS transistor and the drain of a first P-channel MOS transistor, the gate region of said first N-channel MOS transistor being responsive to said first clock pulse train, said first P-channel MOS transistor being responsive to an inverted version of said first clock pulse train; a type II circuit means responsive to said first and third clock pulse trains, respectively, said type II circuit means including a second N-channel MOS transistor, the output terminal of said type II circuit means being connected to the drain region of said second N-channel MOS transistor, the gate region of said second N-channel transistor being responsive to said first clock pulse train, a first logic function circuit means connected on one end to the source region of a second P-channel MOS transistor for performing a gating function, said first logic function circuit means connected at its other end to the drain region of a third P-channel MOS transistor, the drain region of said second P-channel MOS transistor connected to the output terminal of said type II circuit means, said second P-channel MOS transistor being responsive to said third clock pulse train, said third P-channel MOS transistor being responsive to said first clock pulse train; a type III circuit means for performing a NAND logic function, said type III circuit means capable of performing an OR and a NOR logic function, said type III circuit means comprising a complementary MOS inverter circuit; a type IV circuit means including a complementary MOS inverter coupled to the drain region of a third N-channel MOS transistor on one end and to the drain region of a fourth P-channel MOS transistor, said third N-channel MOS transistor being responsive to said second clock pulse train, said fourth P-channel MOS transistor being responsive to an inverted version of said second clock pulse train; a type V circuit means including a fourth N-channel MOS transistor responsive to said second clock pulse train, the output terminal of said type V being connected to the drain region of said fourth N-channel MOS transistor, a second logic function circuit means, including a fifth P-channel MOS transistor for performing an AND logic function, said second logic function circuit means capable of performing an OR logic function and being connected to the output terminal of said type V circuit means on one end and to the drain region of a sixth P-channel MOS transistor on the other end, said sixth P-channel MOS transistor being responsive to said second clock pulse train; a type VI circuit means including a fifth N-channel MOS transistor responsive to said second clock pulse train, the drain region of said fifth N-channel transistor connected to an output terminal of said type VI circuit means, a third logic function circuit means including a seventh P-channel MOS transistor for performing an AND logic function, said third logic function circuit means capable of performing on OR and an AND-OR logic function, and being connected to the output terminal of said type VI circuit means on one end and to the drain region of an eighth P-channel transistor being responsive to a said third clock pulse train; said type I circuit means connected to be driven by receipt of an output signal from said type IV circuit means and said type V circuit means; said first logic function circuit means of said type II circuit means connected to be driven by receipt of an output signal from said type IV, said type V, and said type VI circuit means; said type IV circuit means connected to be driven by receipt of an output signal from said type I and said type II circuit means; said second logic function circuit means of said type V circuit means connected to be driven by receipt of an output from said type IV circuit means; said third logic function circuit means of the type VI circuit means connected to be driven by receipt of an output signal from said type IV and said type V circuit means; and first and second ones of said type III circuit means connected to be driven by an output signal from said type V circuit means and said type VI circuit means, respectively, said first type III circuit means generating a first output signal, said second type III circuit means generating a second output signal, said second logic function circuit means of said type V circuit means connected to be driven by said first output signal, said third logic function circuit means of said type VI circuit means connected to be driven by said second output signal; said clock means driving said type I-VI circuit means.