Frequency synthesizer having a loop filter with a high cut-off frequency

Claim 1

A frequency synthesizer comprising a phase-locked loop having, in this order, at least a voltage-controlled oscillator (VCO), a first divider with an adjustable division factor n or n+1, n being an integer, a second divider the division factor of which is a programmable integer M, a phase comparator and a low-pass filter, the output signal of this second divider and a reference signal having a frequency F being applied to said phase comparator for generating an output signal which is applied as control voltage to the voltage-controlled oscillator via the low-pass filter, the frequency synthesizer further comprising a first digital loop having a first pulse counter, for counting the input pulses of the said second divider and being restarted from its initial counting position by each output pulse of the second divider, and a first comparison device to which the counting position of said first counter and a digital numerical value u, which is adjustable by means of a first adjusting device, are applied for generating a control signal for controlling said first divider so that the size of the frequency steps is equal to the reference frequency F, as well as a second digital loop having a second pulse counter, counting the output pulses of the said second divider, and a second comparison device to which the counting position of the said second pulse counter and a digital numerical value, which is adjustable by means of a second adjusting device, are applied for generating a control signal for controlling said first divider so that the size of the frequency steps is equal to z, z being of such a value that F is a multiple thereof to obtain a division into decimal steps, characterized in that the frequency synthesizer further comprises a third digital loop for generating frequency steps having a size equal to y, y being of such a value that F is a multiple thereof, this third digital loop comprising a third pulse counter (modulo-F/y) for counting the output pulses of said second divider, and a third comparison device which compares the counting position a of the said third counter with a digital numerical value r, which is adjustable by means of a third adjusting device, for generating an output signal which increases the numerical value u in said first adjusting device by one unit for each time the position a is smaller than or equal to the numerical value r.