Detector circuit with integrating feedback means

Claim 2

In an electrical circuit having a signal source, an envelope detecting circuit comprising: envelope detecting means having an input connection at a first node and having an output connection at a second node, said detecting means unidirectionally conducting current between the first and second node responsive to potential at the first node; means for applying signal from the signal source to the first node, including a first capacitor for blocking d-c; means for integrating at least a portion of the potential at the second node to provide integrated potential; and means for applying a portion of the integrated potential to the first node to counteract a tendency for d-c shifts thereat.

Claim 3

An electrical circuit as set forth in claim 1 wherein the means for integrating the potential at the second node and for applying a portion of the integrated potential to the first node includes: a differential-input amplifier having a non-inverting input connected to the second node, having an inverting input and having an output connection; direct coupled feedback means from the output connection of the differential-input amplifier to its inverting input connection; a second capacitor having a first plate connected to a point of fixed potential and having a second plate; means connecting the second plate of the second capacitor to the inverting input of the differential-input amplifier; and a pn junction having a first end connected to the first node and a second end connected to the second plate of the capacitor, said pn junction poled to conduct in an alternate direction to the peak detecting means relative to the first node.

Claim 4

An electrical circuit as set forth in claim 1 wherein the means for integrating the potential at the second node and for applying a portion of the integrated potential to the first node includes: a buffer amplifier having an input connection for receiving signal from the second node and having an output connection for supplying potential directly related to that appearing at its input connection; a second capacitor having a first plate connected to a point of fixed potential and having a second plate; means connecting the output connection of the buffer amplifier to the second plate of the second capacitor; and a pn junction having a first end connected to the first node and a second end connected to the second plate of the second capacitor, said pn junction poled to conduct in an alternate direction to the peak detecting means relative to the first node.

Claim 5

An electrical circuit as set forth in claims 2 or 3 wherein the pn junction comprises a diode.

Claim 6

An electrical circuit as set forth in claims 2 or 3 wherein the pn junction comprises the base-emitter junction of a bipolar transistor.

Claim 7

An envelope detecting circuit comprising: a first capacitor having a first plate connected to a source of time varying signal and having a second plate, connected to a first node; a detecting pn junction having a first end connected at the first node and having a second end connected to a second node for supplying output singal responsive to the envelope defined by signal peaks of a particular polarity at said first node; a second capacitor connected between the second node and a point of fixed potential; means for integrating at least a portion of the potential at the second node and providing an integrated potential; and means for applying a portion of said integrated potential to the first node.

Claim 8

An envelope detecting circuit comprising: a first capacitor having a first plate connected to a source of time varying signal and having a second plate, connected to a first node; a detecting pn junction having a first end connected at the first node and having a second end connected to a second node for supplying output singal responsive to the envelope defined by signal peaks of a particular polarity at said first node; a second capacitor connected between the second node and a point of fixed potential; means for integrating at least a portion of the potential at the second node and providing an integrated potential; and means for applying a portion of said integrated potential to the first node.

Claim 9

An envelope detecting circuit as set forth in claim 6 wherein the means for integrating the potential at the second node and for applying a portion of the integrated potential to the first node includes: a buffer amplifier having an input connection for receiving signal from the second node and having an output connection; a further capacitor having a first plate connected to a point of fixed potential and having a second plate; means connecting the output connection of the buffer amplifier to the second plate of the further capacitor; a further pn junction having a first end connected to the first node and having a second end connected to the second plate of the further capacitor, said further pn junction poled to conduct in an alternate direction to the detecting pn junction relative to the first node.

Claim 10

An envelope detecting circuit as set forth in claim 6 wherein the means for integrating the potential at the second node and for applying a portion of the integrated potential to the first node includes; a differential-input amplifier having a non-inverting input connected to the second node, and having an inverting input connected via direct coupled feedback means to an output connection; a further capacitor having a first plate connected to a point of fixed potential and having a second plate; means connecting the inverting input of the differential-input amplifier to the second plate of the further capacitor; and a further pn junction having a first end connected to the first node and having a second end connected to the second plate of the further capacitor, said pn junction poled to conduct in an alternate direction to the detecting pn junction relative to the first node.

Claim 11

A peak detecting circuit as set forth in claims 7 and 8 wherein the further pn junction comprises a diode.

Claim 12

A peak detecting circuit as set forth in claims 7 and 8 wherein the further pn junction comprises the base-emitter junction of a bipolar transistor.