Patent US4806621A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4258078A Expired / Lapsed US ⏱️ 0.0 years remaining

Metallization for integrated circuits

Assignee: AT&T Inc
•
Filing: 1979-12-21
•
Granted: 1981-03-24
•
Expires: 1999-12-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The sharp features that appear on metallization patterns defined by conventional etching processes can be eliminated by instantaneous melting with short laser pulses. Flow is minimized due to the brevity of the lifetime of the molten state but surface tension removes the sharp corners. With polysilicon metallization conductivity is also improved.

Inventors

  • 👤 George K. Celler
  • 👤 Thomas E. Seidel

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 17:40
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/90; H10P34/00; H10P34/40; H10P34/42; H10P95/04; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/062; H10W20/067; H10W20/068; H10W20/40; H10W20/49; H10W20/493; H10W20/494; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49156

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 126 words
A method for making integrated circuits comprising: forming at least portions of a multiplicity of devices in a semiconductor wafer, forming conductive interconnections between two or more devices by the steps of: applying a uniform coating of conductive material over a substantial portion of the wafer, lithographically masking the wafer over the desired interconnections leaving unwanting portions unmasked, and removing the unwanted portions to form a metallization pattern, the improvement comprising the further step of shaping the edges and/or corners of the metallization pattern by exposing them to laser or electron beam radiation, of sufficient power to melt the conductive material at said edges and/or corners for a period of time, said period of time being short enough to avoid substantial flow of the conductive material.
Claim 2
Independent Claim 126 words
A method for making integrated circuits comprising: forming at least portions of a multiplicity of devices in a semiconductor wafer, forming conductive interconnections between two or more devices by the steps of: applying a uniform coating of conductive material over a substantial portion of the wafer, lithographically masking the wafer over the desired interconnections leaving unwanting portions unmasked, and removing the unwanted portions to form a metallization pattern, the improvement comprising the further step of shaping the edges and/or corners of the metallization pattern by exposing them to laser or electron beam radiation, of sufficient power to melt the conductive material at said edges and/or corners for a period of time, said period of time being short enough to avoid substantial flow of the conductive material.
Claim 3
Dependent Claim 13 words
The method of claim 1 in which the conductive material is a metal.
Claim 4
Dependent Claim 12 words
The method of claim 2 in which the conductive material is polysilicon.
Claim 5
Dependent Claim 11 words
The method of claim 1 in which the substrate comprises silicon.
Claim 6
Dependent Claim 22 words
The method of claim 1 including the further step of forming a second level of metallization over the metallization shaped by melting.
Claim 7
Dependent Claim 21 words
The method of claim 1 in which the step of melting the conductive material increases the sheet conductivity of the material.
Claim 8
Independent Claim 113 words
A method for making integrated circuits comprising: forming at least potions of a multiplicity of devices in a semiconductor wafer, forming conductive interconnections between two or more of the devices by the steps of: applying a uniform coating of conductive material over a substantial portion of the wafer, lithographically masking the wafer over the desired interconnections leaving unwanted portions unmasked, and removing the unwanted portions to form a metallization pattern, the invention characterized by the further step of exposing the conductive material to radiation from an electron beam or laser at a power level and for a time sufficient to increase the sheet conductivity of the conductive material by a least 10 percent.
Claim 9
Independent Claim 113 words
A method for making integrated circuits comprising: forming at least potions of a multiplicity of devices in a semiconductor wafer, forming conductive interconnections between two or more of the devices by the steps of: applying a uniform coating of conductive material over a substantial portion of the wafer, lithographically masking the wafer over the desired interconnections leaving unwanted portions unmasked, and removing the unwanted portions to form a metallization pattern, the invention characterized by the further step of exposing the conductive material to radiation from an electron beam or laser at a power level and for a time sufficient to increase the sheet conductivity of the conductive material by a least 10 percent.
Claim 10
Dependent Claim 12 words
The method of claim 7 in which the conductive material is polysilicon.
Claim 11
Dependent Claim 21 words
The method of claim 3 in which the pulse is a laser pulse with a duration of less than 0.5 microsec.
Claim 12
Dependent Claim 16 words
The method of claim 9 in which the laser pulse is produced by a Nd:YAG laser.
Claim 13
Dependent Claim 18 words
The method of claim 1 in which the lifetime of the molten condition is less than 10 microsec.
Claim 14
Dependent Claim 14 words
The method of claim 1 in which the laser or electron beam is pulsed.
Claim 15
Dependent Claim 29 words
The method of claim 1 wherein the metallization pattern is covered with an insulating layer or a masking layer while being exposed to the laser or electron beam radiation.

References Cited (Backward Citations)

US4000334A Cited
US3909583A Cited
US3838288A Cited
US4082958A Cited
US4159686A Cited
US4117177A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-03-23 1984-09-22 1985-03-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-03-23 1988-09-22 1989-03-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-03-23 1992-09-22 1993-03-24 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag