Patent EP0381655A2 successfully refreshed from Google Patents.
US4257435A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mischief preventing device for a coin sorting machine
Assignee: Fuji Electric Co Ltd
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Filing: 1978-06-06
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Granted: 1981-03-24
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Expires: 1998-06-06
Abstract
Abstract Erroneous counting of both false coins and real coins tied to a string is prevented by providing a two stage counter with a gate in the middle. The first stage determines whether the coin is real and, if real, what its value is. If the coin is real a gate is opened and the coin passes a detector which shuts the gate while simultaneously counting the coin value from the first stage.
Inventors
- 👤 Akio Tanaka
- 👤 Yoshihisa Nakajima
- 👤 Shinji Yokomori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:41
CPC Classifications
G; G07; G07D; G07D3/00; G07D3/14; G07D3/16
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
414 words
In a coin sorting and counting apparatus of the type including: coin sorting means for producing first and second coin sorting signals representing first and second true coin values, respectively, and for producing no coin sorting signal for a false coin; first coin detecting means located upstream of said coil sorting means for producing a first coin detection signal upon the passage of a coin; second coin detecting means located downstream of said coin sorting means for producing a second coin detection signal upon passage of a coin; first gate means located downstream of said second detecting means and responsive to the simultaneous occurrence of a true coin sorting signal and said second coin detection signal to direct a coin along a true coin path; the improvement comprising: first and second flip-flop means for respectively storing first and second coin sorting signals which occur in the interval between the occurrences of said first and second coin detection signal; third flip-flop means settable in a first state in response to the simultaneous occurrence of said second coin detection signal and a stored coin sorting signal in either of said first and second flip-flop means for producing a first gate control signal to open said first gate means to direct a coin along said true coin path; third coin detection means located in said true coin path for producing a third coin detection signal upon the passage of a coin; fourth flip-flop means having set and reset inputs and set and reset outputs; means supplying said first and second coin sorting signals to said set and reset inputs, respectively; first AND circuit means having two inputs coupled to said set output and to said third detection signal, respectively, for producing a first coin counting signal upon each simultaneous occurrence of a first coin sorting signal and a third coin detection signal; second AND circuit means having two inputs coupled to said reset output and to said third detection signal, respectively, for producing a second coin counting signal upon each simultaneous occurrence of a second coin sorting signal and a third coin detection signal; coin counting means for respectively counting the number of said first and second coin counting signals; and means for applying said third coin detection signal to said third flip-flop means to reset it to a second state thereby removing said first gate control signal and closing said first gate means so that a counted coin cannot be withdrawn from said true coin path.
Claim 2
Dependent Claim
414 words
In a coin sorting and counting apparatus of the type including: coin sorting means for producing first and second coin sorting signals representing first and second true coin values, respectively, and for producing no coin sorting signal for a false coin; first coin detecting means located upstream of said coil sorting means for producing a first coin detection signal upon the passage of a coin; second coin detecting means located downstream of said coin sorting means for producing a second coin detection signal upon passage of a coin; first gate means located downstream of said second detecting means and responsive to the simultaneous occurrence of a true coin sorting signal and said second coin detection signal to direct a coin along a true coin path; the improvement comprising: first and second flip-flop means for respectively storing first and second coin sorting signals which occur in the interval between the occurrences of said first and second coin detection signal; third flip-flop means settable in a first state in response to the simultaneous occurrence of said second coin detection signal and a stored coin sorting signal in either of said first and second flip-flop means for producing a first gate control signal to open said first gate means to direct a coin along said true coin path; third coin detection means located in said true coin path for producing a third coin detection signal upon the passage of a coin; fourth flip-flop means having set and reset inputs and set and reset outputs; means supplying said first and second coin sorting signals to said set and reset inputs, respectively; first AND circuit means having two inputs coupled to said set output and to said third detection signal, respectively, for producing a first coin counting signal upon each simultaneous occurrence of a first coin sorting signal and a third coin detection signal; second AND circuit means having two inputs coupled to said reset output and to said third detection signal, respectively, for producing a second coin counting signal upon each simultaneous occurrence of a second coin sorting signal and a third coin detection signal; coin counting means for respectively counting the number of said first and second coin counting signals; and means for applying said third coin detection signal to said third flip-flop means to reset it to a second state thereby removing said first gate control signal and closing said first gate means so that a counted coin cannot be withdrawn from said true coin path.
Claim 3
Dependent Claim
90 words
The improvement as claimed in claim 1 further comprising: second gate means for selectively directing counted coins along first and second paths, respectively, in accordance with their denominations; fifth flip-flop means having set and reset inputs coupled to said first and second counting signals, respectively, and producing a second gate control signal in response to only one of said counting signals; and means for supplying said second gate signal to said second gate means to cause it to direct a counted coin along one of said first and second paths.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-03-23 | 1984-09-22 | 1985-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-03-23 | 1988-09-22 | 1989-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-03-23 | 1992-09-22 | 1993-03-24 | $7700.00 | Window Closed / Lapsed |