Recognition memory with multiwrite and masking

Claim 2

In combination in an associative memory, a plurality of random access memories each including plural random access memory modules comprising an enable port and plural information storage addresses, plural comparator means each connected to a different one of said random access memories for receiving information read out therefrom, data bus means connected to each of said memories and each of said comparator means, memory accessing means including common address bus means connected to said memories, each of said comparator means including means for comparing the information supplied thereto with information present on said data bus means and for developing an output signal representing the results of said comparison, means for storing said output result signals of said comparator means, bit mask register means including plural outputs, and masking logic means connecting said bit mask register outputs and said memory module enable ports for selectively enabling and disabling said memory module depending upon the outputs of said bit mask register means.

Claim 3

A combination as in claim 1 further comprising read gate means connecting the output of each random access memory module with said data bus means.

Claim 4

A combination as in claim 1 further comprising recognition logic means and comparison gate means serially connecting said comparator means with said data bus means.

Claim 5

A combination as in claim 3 wherein said comparator means comprises means for producing an output signal specifying whether or not the information supplied thereto from an associated random access memory module is equal to data present on said data bus means connected thereto, and where said storing means comprises bistable means connected to said comparator means for registering therein the comparison results produced by said comparator means.

Claim 6

A combination as in claim 1 wherein said random access memories are subdivided into subsets, and wherein said memory accessing means includes plural address decoding means each associated with a different random access memory subset connected to and responsive to said common address bus means for selectively enabling a selected one of said random access memory modules in said random access memory subset associated therewith.

Claim 7

A combination as in claim 1 wherein each of said random access memories comprises read and write control port means, read-write control conductor means connected to said read-write control ports of said random access memory modules, and means for selectively inverting a write command to thereby impress a read command on said read-write conductor means.

Claim 8

A combination as in claim 6 further comprising operational mode means for registering therein whether a read or write, or an associative memory function is required, said selective inverting means being connected to said operational mode means for selectively inverting a write command depending upon the state of said mode means.

Claim 9

A combination as in claim 1 further comprising central processor means connected to said data bus means and said memory accessing means.

Claim 10

A combination as in claim 8 wherein said data bus means includes separate read and write buses.

Claim 11

A combination as in claim 1 further comprising means for coupling the comparison result signals stored in said storing means to said data bus means.

Claim 12

A combination as in claim 1 further comprising associative mode signalling means connected to said plural random access memories for coincidentally enabling said plural random access memories.

Claim 13

A combination as in claim 1 further comprising multiwrite mode signalling means, and multiwrite logic means having inputs connected to said multiwrite mode signalling means and said output result storing means and an output connected to said random access memories for coincidentally enabling all memories associated with a like comparison result signal stored in said output result signal storing means.

Claim 14

In combination in an associative memory, a plurality of random access memories each including plural random access memory modules comprising an enable port and plural information storage addresses, plural comparator means each connected to a different one of said random access memories for receiving information read out therefrom, data bus means connected to each of said memories and each of said comparator means, memory accessing means including common address bus means connected to said memories, each of said comparator means including means for comparing the information supplied thereto with information present on said data bus means and for developing an output signal representing the results of said comparison, means for storing said output result signals of said comparator means, multiwrite mode signalling means, and multiwrite logic means having inputs connected to said multiwrite mode signalling means and said output result storing means and an output connected to said random access memories for coincidentally enabling all memories associated with a like comparison result signal stored in said output result signal storing means.

Claim 15

In combination in an associative memory, a plurality of random access memories each including plural random access memory modules comprising an enable port and plural information storage addresses, plural comparator means each connected to a different one of said random access memories for receiving information read out therefrom, data bus means connected to each of said memories and each of said comparator means, memory accessing means including common address bus means connected to said memories, each of said comparator means including means for comparing the information supplied thereto with information present on said data bus means and for developing an output signal representing the results of said comparison, means for storing said output result signals of said comparator means, multiwrite mode signalling means, and multiwrite logic means having inputs connected to said multiwrite mode signalling means and said output result storing means and an output connected to said random access memories for coincidentally enabling all memories associated with a like comparison result signal stored in said output result signal storing means.