US4257018A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic tuning circuits for voltage controlled filters, by digital phase control
Assignee: Leonardo SpA
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Filing: 1979-04-04
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Granted: 1981-03-17
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Expires: 1999-04-04
Abstract
Abstract Automatic tuning circuit for voltage controlled filters, by digital phase control, including an oscillator and a path to be filtered associated with the voltage controlled filter, wherein the voltage controlled filter must be adjusted on a frequency equal or shifted by a preset amount with respect to the oscillator frequency, including means to scan the filter response while it is fed by the signal of the oscillator, means to detect the shift (positive or negative) of the filter response with respect to the oscillator frequency, means to measure in a digital way such a shift and arranged to provide a signal to correct the filter response, and means for digital storage of that correction signal.
Inventors
- 👤 Arturo Masdea
- 👤 Giuseppe Quagliarello
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:23
CPC Classifications
H; H03; H03J; H03J7/00; H03J7/18; H03J7/20; H03J7/28; H03H; H03H21/00; H03J7/02; H03J7/04; H03J7/06
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
512 words
A circuit for automatically tuning a voltage controlled filter to which the output of an oscillator is applied, said circuit comprising a clock generator for generating clock pulses; a divider circuit connected to the clock generator output for dividing the clock pulses to provide a square wave signal at a lower frequency; a sawtooth circuit connected to receive the square wave signal and to transform the same into a sawtooth signal; a first adder circuit having a first input connected to receive the sawtooth signal, a second input, and an output adapted for connection to the voltage controlled filter for scanning the response of the filter; a radio frequency detector adapted for connection to the output of the filter; a squaring circuit connected to said detector for squaring the output thereof; a switching circuit capable alternatively of assuming a first state in which an output signal is supplied and a second state in which no output signal is supplied, said switching circuit having a first input connected to the output of said divider circuit for receipt of the square wave signal and a second input connected to the output of said squaring circuit for receipt of the squared output, said switching circuit responsive to a signal at its first input for assuming its first state and responsive to a signal at its second input for assuming its second state; a first gating circuit having a first input connected to said clock generator output and a second input connected to said switching circuit output and responsive to simultaneous signals at its first and second inputs for generating an output signal; a first counting circuit connected to the output of said first gating circuit; a second gating circuit having a first input connected to said clock generator output and a second input connected to said squaring circuit for receipt of the squared output and responsive to simultaneous signals at its first and second inputs for generating an output signal; a second counting circuit connected to the output of said second gating circuit; a divide by two circuit having an input connected to the output of said second counter; a subtractor circuit having a first input connected to the output of said first counting circuit and a second input connected to the output of said divide by two circuit; a second adder circuit having a first input connected for receipt of the output of said subtractor circuit, a second input, and an output; a register having a first input connected to said second adder circuit output, a second input connected to the output of said divider circuit, and an output connected to said second adder circuit second input; a digital-to-analog converter having an input connected to the output of said register and an output; a third adder circuit having a first input connected to the output of said digital-to-analog converter, a second input adapted for connection to the oscillator, a third input adapted for connection to a source of frequency offset voltage, and an output connected to the second input of said first adder circuit.
Claim 2
Dependent Claim
512 words
A circuit for automatically tuning a voltage controlled filter to which the output of an oscillator is applied, said circuit comprising a clock generator for generating clock pulses; a divider circuit connected to the clock generator output for dividing the clock pulses to provide a square wave signal at a lower frequency; a sawtooth circuit connected to receive the square wave signal and to transform the same into a sawtooth signal; a first adder circuit having a first input connected to receive the sawtooth signal, a second input, and an output adapted for connection to the voltage controlled filter for scanning the response of the filter; a radio frequency detector adapted for connection to the output of the filter; a squaring circuit connected to said detector for squaring the output thereof; a switching circuit capable alternatively of assuming a first state in which an output signal is supplied and a second state in which no output signal is supplied, said switching circuit having a first input connected to the output of said divider circuit for receipt of the square wave signal and a second input connected to the output of said squaring circuit for receipt of the squared output, said switching circuit responsive to a signal at its first input for assuming its first state and responsive to a signal at its second input for assuming its second state; a first gating circuit having a first input connected to said clock generator output and a second input connected to said switching circuit output and responsive to simultaneous signals at its first and second inputs for generating an output signal; a first counting circuit connected to the output of said first gating circuit; a second gating circuit having a first input connected to said clock generator output and a second input connected to said squaring circuit for receipt of the squared output and responsive to simultaneous signals at its first and second inputs for generating an output signal; a second counting circuit connected to the output of said second gating circuit; a divide by two circuit having an input connected to the output of said second counter; a subtractor circuit having a first input connected to the output of said first counting circuit and a second input connected to the output of said divide by two circuit; a second adder circuit having a first input connected for receipt of the output of said subtractor circuit, a second input, and an output; a register having a first input connected to said second adder circuit output, a second input connected to the output of said divider circuit, and an output connected to said second adder circuit second input; a digital-to-analog converter having an input connected to the output of said register and an output; a third adder circuit having a first input connected to the output of said digital-to-analog converter, a second input adapted for connection to the oscillator, a third input adapted for connection to a source of frequency offset voltage, and an output connected to the second input of said first adder circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-03-16 | 1984-09-15 | 1985-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-03-16 | 1988-09-15 | 1989-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-03-16 | 1992-09-15 | 1993-03-17 | $7700.00 | Window Closed / Lapsed |