Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
225 words
A logic system comprising first and second identical logic circuit building blocks, each referred to as an M Circuit, which responds to transitions of a two level, binary input signal to provide a memory and a logic function which has a complete truth table for every possible combination of input signal transitions or changes in logic level at a pair of input terminals A and B, each of said M Circuits comprising: gating means having two inputs connected to said A and B input terminals, respectively; and a set-reset flip flop means having its set input connected to the output of said gating means, its reset input connected to said B input terminal and its set and reset outputs connected respectively to output terminal Q and Q of said M Circuit, said Q and Q output terminals providing complementary binary outputs for any combination of binary inputs applied at said A and B input terminals, whereby said M Circuit is a four terminal device which responds to each transition of said input signal at said A and B terminals to provide outputs at said Q and Q terminals in accordance with its truth table function; and means interconnecting one of said Q and Q output terminals of said first M Circuit with one of said A and B input terminals of said second M Circuit.
Claim 2
Dependent Claim
225 words
A logic system comprising first and second identical logic circuit building blocks, each referred to as an M Circuit, which responds to transitions of a two level, binary input signal to provide a memory and a logic function which has a complete truth table for every possible combination of input signal transitions or changes in logic level at a pair of input terminals A and B, each of said M Circuits comprising: gating means having two inputs connected to said A and B input terminals, respectively; and a set-reset flip flop means having its set input connected to the output of said gating means, its reset input connected to said B input terminal and its set and reset outputs connected respectively to output terminal Q and Q of said M Circuit, said Q and Q output terminals providing complementary binary outputs for any combination of binary inputs applied at said A and B input terminals, whereby said M Circuit is a four terminal device which responds to each transition of said input signal at said A and B terminals to provide outputs at said Q and Q terminals in accordance with its truth table function; and means interconnecting one of said Q and Q output terminals of said first M Circuit with one of said A and B input terminals of said second M Circuit.
Claim 3
Dependent Claim
41 words
System as recited in claim 1 wherein said means interconnecting one of said Q and Q output terminals of said first M Circuit with one of said A and B input terminals of said second M Circuit comprises a delay means.
Claim 4
Dependent Claim
41 words
System as recited in claim 1 wherein said means interconnecting one of said Q and Q output terminals of said first M Circuit with one of said A and B input terminals of said second M Circuit comprises a feedback network.
Claim 5
Dependent Claim
67 words
System as recited in claim 1 wherein a first one of said M Circuits is connected to a second one of said M Circuits by means connecting the B input terminal of said second M Circuit to one of the Q and Q outputs of said first M Circuit whereby said second M Circuit may be reset or enabled to be set by said first M Circuit.
Claim 6
Dependent Claim
26 words
System as recited in claim 1, wherein the Q terminal of a first M Circuit is coupled to the A terminal of a second M Circuit.
Claim 7
Dependent Claim
26 words
System as recited in claim 1, wherein the Q terminal of a first M Circuit is coupled to the A terminal of a second M Circuit.