US4253188A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock synchronization for data communication receiver
Assignee: Ford Motor Co
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Filing: 1979-06-07
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Granted: 1981-02-24
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Expires: 1999-06-07
Abstract
Abstract With respect to a synchronous communications receiver, this specification discloses a decoder for generating a clock signal to synchronize the receiver with the information data rate of the received signal. The implementation of a decoder apparatus as a periodic finite state machine allows a clock signal to be extracted from the energy or transitions of the encoded signal. Such a decoder can define clock information over a large range of data rates. A bandpass filter tuned to the characteristic frequency being received can be coupled to the input of the decoder to limit the synchronization range to that desired by the receiver.
Inventors
- 👤 Melvin G. Gable
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:52
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
65 words
A synchronous data communication receiver adapted to be connected to a communication medium, said receiver comprising: a decoding means for performing a decoding process by extracting signal information from a received signal with code redundancy wherein a periodic finite state machine is used to provide synchronous timing information thereby eliminating the need for an oscillator timing means for generating internal timing to the decoder process.
Claim 2
Dependent Claim
65 words
A synchronous data communication receiver adapted to be connected to a communication medium, said receiver comprising: a decoding means for performing a decoding process by extracting signal information from a received signal with code redundancy wherein a periodic finite state machine is used to provide synchronous timing information thereby eliminating the need for an oscillator timing means for generating internal timing to the decoder process.
Claim 3
Dependent Claim
34 words
A synchronous data communication receiver as recited in claim 1 wherein: said decoding means includes energy filter means whereby the energy in the waveform is used to provide timing information to the decoder process.
Claim 4
Dependent Claim
39 words
A synchronous data communication receiver as recited in claim 1 wherein: said decoding means includes amplitude detector means whereby the amplitude encoding of the code redundancy in the waveform is used to provide timing information to the decoder process.
Claim 5
Dependent Claim
35 words
A synchronous data communication receiver as recited in claim 1 wherein: said decoding means includes phase detector means whereby the phase encoding in the waveform is used to provide timing information to the decoder process.
Claim 6
Dependent Claim
35 words
A synchronous data communication receiver as recited in claim 1 wherein: said decoding means includes frequency detector means whereby the frequency encoding of the waveform is used to provide timing information to the decoder process.
Claim 7
Dependent Claim
35 words
A synchronous data communication receiver as recited in claim 1 wherein: said decoding means includes a bandpass filter means for limiting the synchronization range of said decoder to a predetermined range desired by the receiver.
Claim 8
Dependent Claim
43 words
A synchronous data communication receiver as recited in claim 1 wherein said periodic finite state machine has a plurality of states to determine the synchronous data communication receiver's decoded output, transition through only one of said states defining the receiver's data clock signal.
Claim 9
Dependent Claim
291 words
A synchronous data communication receiver as recited in claim 7 wherein said periodic finite state machine has four states, S0, S1, S2 and S3 and said state machine is adapted to process an input sequence which is ternary, -1, 0, +1, said periodic finite state machine sequentially switching among said four states, state S0 producing a clock output so that leaving state S0 causes a data clock to go from a low to a high state and returning to state S0 from any other state causes the data clock to go from the high state to its low state; said periodic finite state machine having an output of 1 in state S1, an output of 1 in state S2, an output of 0 in state S3, and an output in state S0 the same as the output of the previous state; state S0 being adapted to receive an input signal and remain in state S0 if the input signal is 0 or -1 and go to state S1 if the input signal is +1; state S1 being adapted to receive an input signal and remain in state S1 if the input signal is +1, go to state S0 if the input is -1, and go to state S2 if the input signal is 0; state S2 being adapted to receive an input signal and remain in state S2 if the input signal is 0, go to state S0 if the input signal is -1, and go to state S3 if the input signal is +1; and state S3 being adapted to receive an input signal and remain in state S3 if the input signal is either 0 or 30 1, and go to state S0 if the input signal is -1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-02-24 | 1984-08-25 | 1985-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-02-24 | 1988-08-25 | 1989-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-02-24 | 1992-08-25 | 1993-02-24 | $7700.00 | Window Closed / Lapsed |