Method and apparatus for sequencing two digital signals

Claim 2

Method for creating a sequenced signal by continuing a self-timing first signal having alternate data and synchronization portions with a second signal having alternate data and synchronization portions, said synchronization portions of said second signal having a "1" and a "0" pattern identical to the "1" and "0" pattern of said synchronization portion of said first signal, said first signal being coded so that "1" and "0" bits are represented by changes between a first and second signal level, whereby the initial level of each of said synchronization portions of said first signal varies in dependence upon the signal level at the end of the last previous one of said data portions, the improvement comprising the steps of creating a signal level on a predetermined line (52) corresponding to said signal level at said end of said data portion of said first signal; switching said signal level on said predetermined line in accordance with said "1" and "0" pattern of said synchronization portions of said first and second signals throughout said synchronization portion, said switching being controlled by said second signal after a predetermined time instant in said synchronization portion; and thereafter switching said signal level on said predetermined line in accordance with said second signal, whereby said level changes on said predetermined line constitutes said sequenced signal.

Claim 3

A method as set forth in claim 1, wherein said predetermined time in said synchronization portion is the start of said synchronization portion.

Claim 4

A method as set forth in claim 1, wherein said first signal is a biphase mark coded signal and said second signal is a binary coded signal; further comprising the step of generating timing signals (T 0 °, T 90 °) at time instants corresponding to the end and middle of each of said bits in said first signal; and wherein switching said signal level on said predetermined line under control of said second signal comprises switching said signal level in response to timing signals indicative of said middle of said bit only in the presence of a "1" bit in said second signal and in response to a timing signal signifying said end of said bit in the presence of a "0" bit of said second signal.

Claim 5

Apparatus for creating a sequenced signal by continuing a self-timing first signal having alternate data and synchronization portions with a second signal having alternate data and synchronization portions, said snchronization portions of said second signal having a "1" and "0" pattern identical to the "1" and "0" pattern of said synchronization portion of said first signal, said first signal being coded so that "0" and "1" bits are represented by changes between a first and second signal level, whereby the initial level of said synchronization portion of said first signal varies in dependence upon the signal level at the end of the data portion last preceding said synchronization portion, the improvement comprising first means (8) for changing the signal level on a predetermined line (52) in response to level control signals applied thereto; second means (6, 7) connected to said first means for applying level control signals to said first means so that said signal level on said predetermined line corresponds to said signal level at the end of said data portion of said first signal; and third means (2-5, 11) connected to said first means for applying level control signals switching said signal level on said predetermined line in accordance to said "1" said "0" pattern of said synchronization portions of said first and second signals during said synchronization portion, said switching being controlled by said second signal after a predetermined time instant in said synchronization portion, and thereafter applying said level control signals to said first means under control of said second signal.

Claim 6

Apparatus for creating a sequenced signal by continuing a self-timing first signal having alternate data and synchronization portions with a second signal having alternate data and synchronization portions, said snchronization portions of said second signal having a "1" and "0" pattern identical to the "1" and "0" pattern of said synchronization portion of said first signal, said first signal being coded so that "0" and "1" bits are represented by changes between a first and second signal level, whereby the initial level of said synchronization portion of said first signal varies in dependence upon the signal level at the end of the data portion last preceding said synchronization portion, the improvement comprising first means (8) for changing the signal level on a predetermined line (52) in response to level control signals applied thereto; second means (6, 7) connected to said first means for applying level control signals to said first means so that said signal level on said predetermined line corresponds to said signal level at the end of said data portion of said first signal; and third means (2-5, 11) connected to said first means for applying level control signals switching said signal level on said predetermined line in accordance to said "1" said "0" pattern of said synchronization portions of said first and second signals during said synchronization portion, said switching being controlled by said second signal after a predetermined time instant in said synchronization portion, and thereafter applying said level control signals to said first means under control of said second signal.

Claim 7

Apparatus as set forth in claim 4, wherein said time instant in said synchronization portion is the start of said synchronization portion.

Claim 8

Apparatus as set forth in claim 4, wherein said first signal is a biphase mark coded signal and said second signal is a binary coded signal; further comprising means (32) for generating first and second timing signals respectively indicative of the start and middle of a bit cell in said first signal; and wherein said third means comprises means for furnishing a level control signal switching said level on said predetermined line in response to joint presence of said second timing signal and a "1" bit in said second signal, and in response to a "0" bit of said second signal in the presence of said first timing signal.

Claim 9

Apparatus as set forth in claim 4, wherein said first means comprises a flip-flop.

Claim 10

Apparatus as set forth in claim 6, further comprising differentiating means (21) for differentiating said first signal and furnishing differentiator output signals indicative of the start and middle of each bit cell in said first signal; means (24) connected to said differentiating means for suppressing said differentiator output signal indicative of said middle of said bit cells, thereby furnishing suppressor output signals indicative of the start of each of said bit cells; and wherein said timing signal furnishing means furnishes said timing signals phase locked to said suppressor output signals while said level switching on said predetermined line is controlled by said first signal.

Claim 11

Apparatus as set forth in claim 8, wherein said data portions of said first and second signals comprise data identifying frames in a television signal; further comprising means for furnishing vertical synchronization signals synchronizing said frames of said television signals, and switch means (30) for connecting said timing signal furnishing means to said suppressor means while said first signal is furnishing said level control signals, and to said vertical synchronization signal furnishing means while said second signal is furnishing said level control signals.