Time division digital switching system with code converting and inverse-converting circuits

Claim 2

A time division digital switching system comprising: a plurality of line circuits; a code converting circuit for receiving first and second digital signals transmitted from two line circuits of said plurality of line circuits, said two line circuits participating in a communication, said code converting circuit producing a third digital signal indicating the mutual relationship between said first and second digital signals; a common bus for distributing said third digital signal given from said code converting circuit to each of said plurality of line circuits; a control memory for storing a plurality of address pairs, one of said address pairs corresponding to said two line circuits participating in said communication; control means for writing the address pair of said two line circuits participating in the communication into said control memory in response to the initiation of the communication, for reading out each of the address pairs stored in said control memory periodically, and for allotting one time slot to said two line circuits so that information is interchanged periodically between said two line circuits participating in said communication by said one address pair derived periodically from said control memory; and a code inverse-converting circuit provided in each of said plurality of line circuits and receiving said third digital signal distributed from said code converting circuit and the digital signal given from the corresponding line circuit for reproducing the digital signal relating to another line circuit identified by one of said address pairs.

Claim 3

A time division digital switching system as claimed in claim 1, wherein said code converting circuit comprises a plurality of input terminals connected respectively to the output terminals of said line circuits, an Exclusive OR circuit having two input terminals and an output terminal connected to said common bus, a switch matrix for connecting said plurality of input terminals with said two input terminals of said Exclusive OR circuit, and a control unit for controlling said switch matrix to transmit said first and second digital signals to each of said two input terminals of said Exclusive OR circuit respectively during said allotted one time slot; wherein said third digital signal is composed of an Exclusive OR output signal between said first and second digital signals; and wherein said code inverseconverting circuit is composed of an Exclusive OR circuit.

Claim 4

A time division digital switching system as claimed in claim 1, wherein said line circuits have first and second output terminals, respectively, wherein said code converting circuit comprises first and second buses connecting said first and second output terminals of said line circuits in common, respectively, and an Exclusive OR circuit having two input terminals connected to said first and second buses and an output terminal connected to said common bus; wherein said third digital signal is an Exclusive OR output between said first and second digital signals; and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 5

A time division digital switching system as claimed in claim 1, wherein said code converting circuit comprises a logic circuit having a plurality of input terminals connected respectively to the output terminals of said line circuits, and a plurality of Exclusive OR circuits; wherein each of said plurality of input terminals is connected to an input terminal of one of said plurality of Exclusive OR circuits; said plurality of Exclusive OR circuits being connected in a multistage form so that the final stage has only one Exclusive OR circuit; the output terminal of said final stage Exclusive OR circuit forms the output terminal of said code converting circuit; wherein said output terminal is connected to said common bus; and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 6

A time division digital switching system as claimed in claim 1, wherein said line circuits have first and second output terminals, respectively, a first transmitting gate for producing at said first output terminal of said two output terminals the logical level "1" in the case of non-communication and a transmitting digital signal in the case of communication, and a second transmitting gate for producing at said second output terminal the logical level "1" in the case of non-communication and an inverted signal corresponding to said transmitting digital signal in the case of communication; wherein said code converting circuit is composed of a first bus connecting all of said first output terminals in said line circuits, a second bus connecting all of said second output terminals in said line circuits, and a logic circuit having two input terminals connected to said first and second buses for producing on said common bus the logical level "1" when both of said two input terminals have the logical level "0", the logical level "0" when either one of said two input terminals has the logical level "1" and the logical level "1" or "0" when both of said two input terminals have the logical level "1"; and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 7

A time division digital switching system as claimed in claim 1, wherein said code converting circuit comprises a plurality of input terminals connected respectively to the output terminals of said line circuits, a digital adder having two input terminals receiving said first and second digital signals each having N bits, respectively, and an output terminal connected to said common bus for producing the lower N bits other than the most significant bit of (N+1) bits which are an addition result between said first and second digital signals as said third digital signal, a switch matrix for connecting a plurality of input terminals connected respectively to the output terminals of said line circuits with said two input terminals of said digital adder, and a control unit for controlling said switch matrix to transmit said first and second digital signals to each of said two input terminals of said digital adder respectively during said allotted one time slot; and wherein said code inverse-converting circuit is composed of a digital subtractor receiving a digital signal having (N+1) bits composed of the most significant bit and the lower N bits in which said most significant bit is "1" and the lower N bits correspond to said third digital signal and the digital signal having N bits transmitted from the corresponding line circuit for subtracting said digital signal having N bits transmitted from the corresponding line circuit from said digital signal having (N+1) bits thereby producing the lower N bits other than the most significant bit of (N+1) bits which are a subtraction result.

Claim 8

A time division digital switching system as claimed in claim 1, wherein said line circuits have first and second output terminals, respectively, wherein said code converting circuit comprises first and second buses for connecting said first and second output terminals of said line circuits in common, respectively, and a digital adder having two input terminals connected to said first and second buses for receiving said first and second digital signals having N bits, respectively, and an output terminal connected to said common bus for producing the lower N bits other than the most significant bit of (N+1) bits which are an addition result between said first and second digital signals as said third digital signal; and wherein said code inverse-converting circuit is composed of a digital subtractor for receiving a digital signal having (N+1) bits composed of the most significant bit and the lower N bits in which said most significant bit is "1" and the lower N bits correspond to said third signal and the digital signal having N bits transmitted from the corresponding line circuit for subtracting said digital signal having N bits transmitted from the corresponding line circuit from said digital signal having (N+1) bits thereby producing the lower N bits other than the most significant bit of (N+1) bits which are a subtraction result.

Claim 9

A time division digital switching system comprising: a plurality of line circuit groups; and a highway switching circuit having a plurality of input terminals and output terminals corresponding to said line circuit groups, respectively, wherein each of said line circuit groups includes: a plurality of line circuits; a code converting circuit for receiving first and second digital signals participating in a communication and transmitted from said line circuits or said highway switching circuit, for producing a third digital signal indicating the mutual relationship between said first and second digital signals and for supplying a digital signal given from a line circuit within the same one of said plurality of line circuit groups to said input terminal of said highway switching circuit in the case of a communication between line circuit groups; a common bus for distributing said third digital signal derived from said code converting circuit to said respective line circuits within said one of said plurality of line circuit groups; a control memory having a plurality of first address pairs, one of said first address pairs corresponding to two line circuits participating in the case of communication within said one of said plurality of line circuit groups, a plurality of second address pairs, one of each second address pair corresponding to an address with respect to one line circuit within a line circuit group to which said line circuit belongs and the other one of said address pair corresponding to an address with respect to said highway switching circuit in the case of communication between line circuit groups; control means for writing said first or second address of said pair into said control memory in response to the initiation of each communication, for reading out said first or second address of said pair out of said control memory periodically, and for allotting one time slot to said two line circuits in the case of communication within one of said line circuit groups and to one line circuit and said highway switching circuit in the case of communication between line circuit groups, respectively, so that information for the communication between said two line circuits participating in said communication within one of said line circuit groups and said communication between said line circuit groups is interchanged periodically by an address pair derived periodically from said control memory; and a code inverse-converting circuit provided in each of said line circuits for receiving said third digital signal distributed from said code converting circuit and the digital signal given from the corresponding line circuit and for reproducing the digital signal given from another line circuit identified by one of said address pairs.

Claim 10

A time division digital switching system comprising: a plurality of line circuit groups; and a highway switching circuit having a plurality of input terminals and output terminals corresponding to said line circuit groups, respectively, wherein each of said line circuit groups includes: a plurality of line circuits; a code converting circuit for receiving first and second digital signals participating in a communication and transmitted from said line circuits or said highway switching circuit, for producing a third digital signal indicating the mutual relationship between said first and second digital signals and for supplying a digital signal given from a line circuit within the same one of said plurality of line circuit groups to said input terminal of said highway switching circuit in the case of a communication between line circuit groups; a common bus for distributing said third digital signal derived from said code converting circuit to said respective line circuits within said one of said plurality of line circuit groups; a control memory having a plurality of first address pairs, one of said first address pairs corresponding to two line circuits participating in the case of communication within said one of said plurality of line circuit groups, a plurality of second address pairs, one of each second address pair corresponding to an address with respect to one line circuit within a line circuit group to which said line circuit belongs and the other one of said address pair corresponding to an address with respect to said highway switching circuit in the case of communication between line circuit groups; control means for writing said first or second address of said pair into said control memory in response to the initiation of each communication, for reading out said first or second address of said pair out of said control memory periodically, and for allotting one time slot to said two line circuits in the case of communication within one of said line circuit groups and to one line circuit and said highway switching circuit in the case of communication between line circuit groups, respectively, so that information for the communication between said two line circuits participating in said communication within one of said line circuit groups and said communication between said line circuit groups is interchanged periodically by an address pair derived periodically from said control memory; and a code inverse-converting circuit provided in each of said line circuits for receiving said third digital signal distributed from said code converting circuit and the digital signal given from the corresponding line circuit and for reproducing the digital signal given from another line circuit identified by one of said address pairs.

Claim 11

A time division digital switching system as claimed in claim 8, wherein said code converting circuit has a plurality of input terminals connected respectively to the output terminals of said line circuits, another input terminal connected to the output terminal of said highway switching circuit, an output terminal connected to said common bus, another output terminal connected to the input terminal of said highway switching circuit, an Exclusive OR circuit having two input terminals and having an output terminal connected to said output terminal connected to said common bus, a switch matrix for connecting said plurality of input terminals and said another input terminal with the input terminals of said Exclusive OR circuit and said another output terminal, and a control unit for controlling said switch matrix to transmit said first and second digital signals to each of said two input terminals of said Exclusive OR circuit respectively during said allotted one time slot; and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 12

A time division digital switching system as claimed in claim 8, wherein said line circuits have first and second output terminals, respectively, wherein said code converting circuit comprises first and second buses for connecting said first and second output terminals of said line circuits in common, respectively, an Exclusive OR circuit having two input terminals connected to said first and second buses and an output terminal connected to said common bus, a first logic element for supplying the digital signal given from said highway switching circuit to either one of said first bus and said second bus, and a second logic element for supplying the digital signal on the other one of said second bus and said first bus to said highway switching circuit; and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 13

A time division digital switching system as claimed in claim 8, wherein said line circuits have first and second output terminals, respectively, wherein said code converting circuit comprises first and second buses for connecting said first and second output terminals of said line circuits in common, respectively, a first Exclusive OR circuit having input terminals connected to said first and second buses, respectively, and an output terminal connected to the input terminal of said highway switching circuit, and a second Exclusive OR circuit having input terminals connected to the output terminal of said first Exclusive OR circuit and the output terminal of said highway switching circuit and an output terminal connected to said common bus; and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 14

A time division digital switching system as claimed in claim 8, wherein said code converting circuit comprises a logic circuit having a plurality of input terminals connected respectively to the output terminals of said line circuits within said group and a plurality of first Exclusive OR circuits, and a second Exclusive OR circuit having one input terminal connected to the output terminal of said logic circuit and another input terminal connected to the output terminal of said highway switching circuit; wherein each of said plurality of input terminals is connected to an input terminal of one of said plurality of first Exclusive OR circuits; wherein said plurality of first Exclusive OR circuits are connected in a multi-stage form so that the final stage has only one first Exclusive OR circuit; wherein the output terminal of said final stage of the first Exclusive OR circuit forms the output terminal of said logic circuit; wherein said output terminal is connected to the input terminal of said highway switching circuit; wherein said common bus connects the output terminal of said second Exclusive OR circuit with all of the input terminals of said line circuits; and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 15

A time division digital switching system as claimed in claim 8, wherein said code converting circuit comprises a logic circuit having a plurality of input terminals connected to respective ones of the output terminals of said line circuits within said group and the output terminal of said highway switching circuit, a plurality of first Exclusive OR circuits, a second Exclusive OR circuit having one input terminal connected to the output terminal of said logic circuit, another input terminal connected to the output terminal of said highway switching circuit and an output terminal connected to the input terminal of said highway switching circuit; wherein each of said plurality of input terminals is connected to an input terminal of one of said plurality of first Exclusive OR circuits; wherein said plurality of first Exclusive OR circuits are connected in a multi-stage form so that the final stage has only one first Exclusive OR circuit; wherein the output terminal of said final stage of the first Exclusive OR circuit forms the output terminal of said code converting circuit; wherein said common bus connects the output terminal of said logic circuit with all of the input terminals of said line circuits; and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 16

A time division digital switching system as claimed in claim 8, wherein each of said plurality of line circuits has first and second output terminals, an input terminal, a first transmitting gate for supplying to said first output terminal the logic level "1" in the case of non-communication and the transmitting digital signal in the case of communication, and a second transmitting gate for supplying to said second output terminal of said line circuit the logical level "1" in the case of non-communication and an inverted signal corresponding to said transmitting digital signal in the case of communication, wherein said code converting circuit is composed of a first bus for connecting all of the first output terminals of said line circuits; a second bus for connecting all of the second output terminals of said line circuits; a gate circuit having an input terminal connected to the output terminal of said highway switching circuit; a first output terminal connected to said first bus and a second output terminal connected to said second bus; a first common bus transmitting gate for supplying to said first output terminal a logical level "1" in the case of the communication within a group and a digital signal of a line circuit in the other group participating in the communication which is applied to said input terminal in the case of the communication between groups, and a second common bus transmitting gate for supplying to said second output terminal a logical level "1" in the case of the communication within the group and an inverted signal corresponding to said digital signal in the case of the communication between the groups; a logic circuit having two input terminals connected to said first and second buses for producing the logical level "1" when both of said two input terminals have the logical level "0", a logic level "0" when either one of said two input terminals has the logical level "1" and the logical level "1" or "0" when both of said two input terminals have the logical level "1"; and an Exclusive OR circuit having two input terminals, one of which is connected to the output terminal of said logic circuit and the other of which is connected to said output terminal of said highway switching circuit and an output terminal connected to the input terminal of said highway switching circuit, wherein said common bus connects the output terminal of said logic circuit with all of the input terminals of said line circuits, and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 17

A time division digital switching system as claimed in claim 8, wherein each of said plurality of line circuits has first and second output terminals, an input terminal, a first transmitting gate for supplying to said first output terminal the logical level "1" in the case of non-communication, and the transmitting digital signal in the case of communication and a second transmitting gate for supplying to said second output terminal the logical level "1" in the case of non-communication and an inverted signal corresponding to said transmitting digital signal; wherein said code converting circuit is provided in each of said groups and is composed of a first bus for connecting all of the first output terminals of said line circuits, a second bus for connecting all of the second output terminals of said line circuits, a first logic circuit having an input terminal connected to said first bus for producing the applied digital signal as it is in the case of the communication within a group and the logical level "0" in the case of the communication between groups, a second logic circuit having two input terminals connected to said second bus and the output terminal of said first logic circuit and an output terminal connected to the input terminal of said highway switching circuit for producing the logical level "1" when both of said two input terminals have the logical level "0", the logic level "0" when either one of said two input terminals has the logical level "1", and the logical level "1" or "0" when both of said two input terminals have the logical level "1", and a first Exclusive OR circuit having two input terminals, one of which is connected to the output terminal of said second logic circuit and the other of which is connected to the output terminal of said highway switching circuit; wherein said common bus connects the output terminal of said first Exclusive OR circuit with all of the input terminals of said line circuits; and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 18

A time division digital switching system as claimed in claim 8, wherein each of said plurality of line circuits has first and second output terminals, an input terminal, a first transmitting gate for supplying to said first output terminal the logical level "1" in the case of non-communication and the transmitting digital signal in the case of communication, and a second transmitting gate for supplying to said second output terminal of said line circuit a logical level "1" in the case of non-communication and an inverted signal corresponding to said transmitting digital signal; wherein said code converting circuit is composed of a first bus for connecting all of the first input terminals of said line circuits and connected to the input terminal of said highway switching circuit, a second bus for connecting all of the second output terminals of said line circuits, a first logic circuit having two input terminals connected to said first and second buses for producing a logical level "1" when both of said two input terminals have the logical level "0", the logical level "0" when either one of said two input terminals has the logical level "1" and the logical level "1" or "0" when both of said two input terminals have the logical level "1", and a second logic circuit having a first input terminal connected to the output terminal of said first logic circuit, a second input terminal connected to said first bus and a third input terminal connected to the output terminal of said highway switching circuit for producing the signal applied to said first input terminal connected to the output terminal of said first logic circuit in the case of the communication within a group, and an Exclusive OR circuit having its inputs connected to said second and third input terminals for producing an output signal in the case of the communication between the groups; and wherein said common bus connects the output terminal of said second logic circuit with all of the input terminals of said line circuits; and wherein said code inverse-converting circuit is composed of an Exclusive OR circuit.

Claim 19

A time division digital switching system as claimed in claim 8, wherein said code converting circuit is composed of a plurality of input terminals connected respectively to the output terminals of said line circuits, another input terminal connected to the output terminal of said highway switching circuit, an output terminal connected to said common bus, another output terminal connected to the input terminal of said highway switching circuit, a digital adder having two input terminals receiving first and second digital signals having N bits, respectively, for producing the lower N bits other than the most significant bit of (N+1) bits which are an addition result between said first and second digital signals as a third digital signal at said output terminal connected to said common bus, a switch matrix for connecting said plurality of input terminals and said another input terminal with said two input terminals of said digital adder and said another output terminal, and a control unit for controlling said switch matrix to transmit said first and second digital signals to each of said two input terminals of said digital adder respectively during said allotted one time slot; and wherein said code inverse-converting circuit is composed of a digital subtractor receiving a digital signal having (N+1) bits composed of the most significant bit and the lower N bits in which said most significant bit is "1" and the lower N bits correspond to said third digital signal and the transmitting digital signal from the line circuit for subtracting said transmitting digital signal having N bits from the corresponding line circuit from said digital signal having (N+1) bits, thereby producing the lower N bits other than the most significant bit of (N+1) bits which are a subtraction result.