Audio chime-signal generating circuit

Claim 2

An audio chime-signal generating circuit, comprising (a) two oscillators having respective high and low operating frequencies; (b) timing circuitry for switching on said oscillators for respective periods of time and for switching on the low-frequency oscillator after the high frequency oscillator; (c) decay circuitry for causing progressive decay in the output of each oscillator over an end portion of the respective operating periods; and (d) a sine shaping circuit through which the oscillator outputs are passed to remove harmonics of the high and low operating frequencies.

Claim 3

A circuit as claimed in claim 1, in which said timing circuitry comprises a first timer the output of which changes voltage level in response to an initiation, said output being applied to said high frequency oscillator to enable the latter.

Claim 4

A circuit as claimed in claim 1, in which said timing circuitry comprises first and second timers, the output of said first timer changing voltage level in response to an initiation and said output of the second timer changing voltage level in response to and a predetermined interval after the change in level of the first timer output, the respective timer outputs being applied to said high and low frequency oscillators, respectively, to enable the latter.

Claim 5

A circuit as claimed in claim 3, in which said changes in output of said timers activates the respective decay circuits, each decay circuit being effective to terminate the passage of the respective oscillations to said sine shaper after a predetermined interval.

Claim 6

A circuit comprising two oscillators having respective high and low operating frequencies, timing circuitry for switching the oscillators on for respective periods of time and switching the low-frequency oscillator on after the high frequency oscillator, decay circuitry for causing a progressive decay in the output of each oscillator over an end portion of the respective operating periods, and a sine shaping circuit through which the oscillator outputs are passed to remove harmonics of the high and low operating frequencies, in which the timing circuitry comprises first and second timers, the output of said first timer changing voltage level in response to an initiation, and the output of said second timer changing voltage level in response to and a predetermined interval after the change in level of the first timer output, the respective timer outputs being applied to said high and low frequency oscillators, respectively, to enable the latter, in which said changes in output of the timers activate the respective decay circuits, each decay circuit being effective to terminate the passage of the respective oscillations to the sine shaper after a predetermined interval, and in which each decay circuit includes a series connection of a capacitor and resistor, said series connection shunting signal path from the respective oscillator to the sine shaper, the junction of said resistor and said capacitor being connected to the output of the respective timer.

Claim 7

A circuit comprising two oscillators having respective high and low operating frequencies, timing circuitry for switching the oscillators on for respective periods of time and switching the low-frequency oscillator on after the high frequency oscillator, decay circuitry for causing a progressive decay in the output of each oscillator over an end portion of the respective operating periods, and a sine shaping circuit through which the oscillator outputs are passed to remove harmonics of the high and low operating frequencies, in which the timing circuitry comprises first and second timers, the output of said first timer changing voltage level in response to an initiation, and the output of said second timer changing voltage level in response to and a predetermined interval after the change in level of the first timer output, the respective timer outputs being applied to said high and low frequency oscillators, respectively, to enable the latter, in which said changes in output of the timers activate the respective decay circuits, each decay circuit being effective to terminate the passage of the respective oscillations to the sine shaper after a predetermined interval, and in which each decay circuit includes a series connection of a capacitor and resistor, said series connection shunting signal path from the respective oscillator to the sine shaper, the junction of said resistor and said capacitor being connected to the output of the respective timer.

Claim 8

A circuit as claimed in claim 5, in which a diode is provided in said signal path between said oscillator and said decay circuit and becomes reverse biased, to terminate the passage of oscillations, when said capacitor has reached a threshold level of charge after said change in level of the respective timer output.

Claim 9

A circuit as claimed in claim 5, in which a diode is provided in said signal path between said oscillator and said decay circuit and becomes reverse biased, to terminate the passage of oscillations, when said capacitor has reached a threshold level of charge after said change in level of the respective timer output, and in which a second diode is provided in said path, in reverse polarity to said first diode, between said sine shaper and the junction of said path with said series connection, a resistor shunting the output of said second diode and the second diode becoming reverse biased at the same time as the first diode.

Claim 10

A circuit as claimed in claims 3 or 5, in which each timer comprises an operational amplifier.

Claim 11

A circuit as claimed in claim 1 or 5, in which each oscillator comprises an operational amplifier.

Claim 12

A circuit as claimed in claim 1 or 5, further comprising means for activating said second oscillator only to provide a low pitch note alone.

Claim 13

A circuit as claimed in claim 5, further comprising means for activating the second oscillator only to provide a low pitch note alone, said means being effective, in response to initiation thereof, to a change an input of the said second timer so as to change the output level thereof and thereby activate said second oscillator.

Claim 14

A circuit as claimed in claim 11, in which said means is responsive to a positive-going transition at its input to apply this transition to one input of said second timer, and is responsive to a negativegoing transition at its input to apply such transition to another input of said second timer, said second timer comprising an operational amplifier.