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US4249179A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit arrangement for displacing the clutter spectrum in a radar receiver

Assignee: Siemens AG
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Filing: 1978-07-24
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Granted: 1981-02-03
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Expires: 1998-07-24
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Abstract

Abstract A circuit for a pulse Doppler radar receiver in which a measuring signal for determining the mean frequency of disturbing low frequency received clutter signals is obtained from which there is determined a control signal for operating a circuit that precedes the clutter filter and serves to displace the clutter spectrum into the blocking ranges of the fixed clutter filter particularly for radar devices having a non-constantly scanning antenna and wherein the circuit for determining the mean change in the clutter phase is in parallel with a delay device which has a delay that extends over a number of radar periods and wherein the circuit for determining the mean change in the clutter phase is preceded by an adjustable phase shift device which is followed by an accumulator for the addition of phase change and wherein continuous adjustment of an adjustable phase shift device is accomplished with a return loop and in which a switch is provided between the circuit for determining the mean change in the clutter phase and the accumulator which is closed at the end of each radar period for the transmission of measuring values.

Inventors

  • 👤 Peter Kolacny

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 15:09
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/02; G01S7/28; G01S7/285; G01S7/292; G01S7/2923

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 288 words
A circuit arrangement for a receiver of a pulse-Doppler-radar with a fixed clutter filter and with a pre-connected device for the displacement of the clutter spectrum and with a circuit for the determination of the mean change of the phase to prevent interfering low frequency received clutter signals during consecutive radar periods for producing a control signal for displacement of the clutter spectrum, in particular for radar devices with a non-constantly scanning antenna, characterized in that the received clutter signals are supplied by way of two parallel circuit branches to a phase shifting device (PS1) at the output of the circuit arrangement, with one circuit branch containing the circuit for determining the mean change of the clutter phase (MCA) and which is part of a regulating loop and contains a memory (TPA) which is connected to the output of the regulating loop, and the other circuit branch contains a delay line (VE) which has a delay which extends over several (n) radar periods and the regulating loop of the first circuit branch includes in series an adjustable phase shifting device (PS2), the circuit for the determination of the mean change of the clutter phase (MCA), an accumulator (AKU) and a return loop (RFS) from the output of the accumulator (AKU) to the adjustable phase shifting device (PS2) and the circuit for the determination of the mean change of the clutter phase (MCA) and the accumulator (AKU) are connected through a switch (SA1), which is closed at the end of a radar period, and the accumulator (AKU) and the following memory (TPA) are connected through a further switch (SA2) which is closed after a number of several (n) radar periods corresponding to the delay in the delay device (VE).
Claim 2
Dependent Claim 288 words
A circuit arrangement for a receiver of a pulse-Doppler-radar with a fixed clutter filter and with a pre-connected device for the displacement of the clutter spectrum and with a circuit for the determination of the mean change of the phase to prevent interfering low frequency received clutter signals during consecutive radar periods for producing a control signal for displacement of the clutter spectrum, in particular for radar devices with a non-constantly scanning antenna, characterized in that the received clutter signals are supplied by way of two parallel circuit branches to a phase shifting device (PS1) at the output of the circuit arrangement, with one circuit branch containing the circuit for determining the mean change of the clutter phase (MCA) and which is part of a regulating loop and contains a memory (TPA) which is connected to the output of the regulating loop, and the other circuit branch contains a delay line (VE) which has a delay which extends over several (n) radar periods and the regulating loop of the first circuit branch includes in series an adjustable phase shifting device (PS2), the circuit for the determination of the mean change of the clutter phase (MCA), an accumulator (AKU) and a return loop (RFS) from the output of the accumulator (AKU) to the adjustable phase shifting device (PS2) and the circuit for the determination of the mean change of the clutter phase (MCA) and the accumulator (AKU) are connected through a switch (SA1), which is closed at the end of a radar period, and the accumulator (AKU) and the following memory (TPA) are connected through a further switch (SA2) which is closed after a number of several (n) radar periods corresponding to the delay in the delay device (VE).
Claim 3
Dependent Claim 59 words
A circuit arrangement as claimed in claim 1, wherein said circuit (MCA) for determining the mean change in the clutter phase possesses a plurality of relatively wide range zones, and the phase relationship is determined by comparing the received signals from consecutive reception periods in the same range zones, and a mean value is formed from these individual values.

References Cited (Backward Citations)

GB1380040A Cited
US4042924A Cited
US3742500A Cited
US3962704A Cited
US4093949A Cited
US4132990A Cited
US4137533A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-02-03 1984-08-04 1985-02-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-02-03 1988-08-04 1989-02-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-02-03 1992-08-04 1993-02-03 $7700.00 Window Closed / Lapsed

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