Low noise, low phase shift analog signal multiplier

Claim 2

A signal mutiplier comprising: means for forming pulses at an output terminal having heights proportional to signals coupled to a first input means and widths proportional to signals coupled to a second input means; means coupled to said output terminal of said pulse former means for integrating pulses; means for sampling and holding integrated values obtained by said integrator means; means for resetting said integration means; and means responsive to signals received from said pulse former means for generating sample and hold commands to said sample and hold means and reset signals to said integrator reset means and said pulse former means.

Claim 3

A signal multiplier in accordance with claim 1 wherein said command and reset means includes: first monostable multivibrator means triggered by signals received from said pulse former means to provide trigger signals at a first output terminal and to provide sample and hold command signals from a second output terminal to said sample and hold means; and second monostable multivibrator means triggered by said trigger signal at said first output terminal of said first monostable multivibrator means to provide reset signals from a first output terminal to said integrator reset means and to provide reset signals from a second output terminal to said pulse former means.

Claim 4

A signal multiplier in accordance with claims 1 or 2 wherein said pulse former means includes: comparator means having first and second input terminals, said first input terminal coupled to said second input means; means for generating a current; capacitor means coupled to be charged by said current generator means to provide a voltage at said second input terminal of said comparator means, said voltage causing a change of state at the output terminal of said comparator means when it achieves a predetermined level relative to said signals coupled to said first input terminal of said comparator means; toggle means coupled to said output terminal of said comparator means having a predetermined state at a first output terminal and a state complementary to said predetermined state at a second output terminal for changing states existing at said first and second output terminals to complementary states upon the change of state at said output terminal of said comparator means, said second output terminal coupled to said command and reset means whereby upon said change of state at said second output terminal said command and reset means couples reset signals to said integrator reset means, reset signals to said toggle means and sample and hold command signals to said sample and hold means; first switch means coupled to said capacitor means and to said first output terminal of said toggle means for substantially discharging said capacitor when said state at said first output terminal of said toggle means changes from said predetermined state to the complementary state; and second switch means coupled to said first output terminal of said toggle means and to said output terminal of said pulse former means for substantially terminating signals at said output terminal of said pulse former when said state at said first output terminal of said toggle means changes from said predetermined state to the complementary state, thereby forming pulses with heights proportional to said signals at said first input means and widths proportional to said signals at said second input means.

Claim 5

A signal multiplier in accordance with claim 3 further including means coupled to said sample and hold means and said first input means for providing signals representative of the difference between said integrated values sampled and held by said sample and hold means and signals coupled to said first input means.

Claim 6

A signal multiplier in accordance with claim 4 wherein said pulse former means includes summation means having a first input terminal coupled to said second input means, an output terminal coupled to said first input terminal of said comparator means and a second input terminal, said summation means for providing a signal to said first input terminal of said comparator means that is representative of the sum of signals coupled to said second input means and said second input terminal of said summation means.

Claim 7

A signal multiplier in accordance with claims 1 or 2 wherein said pulse former means includes: digital comparator means having first and second input terminal means for receiving digital numbers for providing high level signals at output terminal means whenever a digital number coupled to said first input terminal means from said second input means exceeds a digital number coupled to said second input terminal means; binary counter means having output terminal means coupled to said second input terminal means of said digital comparator means and coupled to receive reset signals from said command and reset means and to receive clock pulses for providing digital numbers at said output terminal means which are representative of the number of pulses received between successive reset signals; toggle means coupled to said output terminal of said comparator means having a predetermined state at a first output terminal and a state complementary to said predetermined state at a second output terminal for changing states existing at said first and second output terminals to complementary states upon the change of state at said output terminal of said comparator means, said second output terminal coupled to said command reset means whereby upon said change of state at said second output terminal, said command and reset means couples reset signals to said integrator reset means, reset signals to said toggle means and sample and hold command signals to said sample and hold means; and switch means coupled to said first output terminal of said toggle means and to said output terminal of said pulse former means for substantially terminating signals at said output terminal of said pulse former when said state at said first output terminal of said toggle means changes from said predetermined state to the complementary state, thereby forming pulses with heights proportional to said signals at said first input means and widths proportional to said signals at said second input means.

Claim 8

A signal multiplier in accordance with claim 3 further including means coupled to said sample and hold means and said first input means for providing signals representative of the difference between said integrated values sampled and held by said sample and hold means and signals coupled to said first input means.

Claim 9

A signal multiplier in accordance with claim 4 wherein said pulse former means includes summation means having a first input terminal coupled to said second input means, an output terminal coupled to said first input terminal of said comparator means and a second input terminal, said summation means for providing a signal to said first input terminal of said comparator means that is representative of the sum of signals coupled to said second input means and said second input terminal of said summation means.