US4245231A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Combination capacitor and transistor structure for use in monolithic circuits
Assignee: Motorola Solutions Inc
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Filing: 1978-12-26
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Granted: 1981-01-13
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Expires: 1998-12-26
Abstract
Abstract A combination capacitor and transistor structure is described wherein the capacitor is formed integrally with the emitter electrode of the transistor. The transistor is formed in a monolithic integrated circuit using generally known techniques and constitutes a vertically integrated PNP device. The emitter electrode of the transistor which comprises a P+ diffusion region is of a predetermined area which is large enough to form the bottom plate of the capacitor. The top plate of the capacitor is formed by growing a dielectric material over the diffused emitter region and then forming metallization thereover. The combination capacitor and transistor structure may be utilized in a bias network for biasing the output stage of an operational amplifier in a class AB mode. The capacitor formed in the combination structure may be utilized as the compensation capacitor in such operational amplifier which utilizes pole splitting techniques. The improvement provided by the invention reduces the surface area of the semiconductor die chip required to form the capacitor and transistor which facilitates greater device density on a particular die chip.
Inventors
- 👤 Robert B. Davies
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:16
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
251 words
In a monolithic integrated circuit having a substrate region of semiconductor material of a first conductivity type, an epitaxial region of semiconductor material of a second conductivity type formed on the substrate region, a portion of the epitaxial region being isolated by an isolation region of semiconductor material of the first conductive type from the remainder thereof wherein an isolation pocket of the epitaxial region is defined, a combination capacitor and transistor structure, the improvement comprising: the isolated epitaxial pocket region having an outwardly planar facing surface and being the base region of the transistor, the substrate region lying under the isolated epitaxial pocket region being the collector region of the transistor; a first defined region of semiconductor material of the first conductivity type formed in the isolated epitaxial pocket region and having an outwardly facing surface coplanar with said outwardly facing surface of said isolated epitaxial pocket region, said first region being the emitter region of the transistor; a layer of dielectric material formed over said first region; a layer of metallic material formed over the dielectric material and said first region; and said layer of metallic material, in combination with said dielectric material and said first region forming a capacitor with said metallic material being a first plate of the capacitor and the active emitter region of the transistor being a second plate of the capacitor wherein the combined capacitor and transistor structure is realized by the capacitor being formed integrally with the active emitter region of the transistor.
Claim 2
Dependent Claim
251 words
In a monolithic integrated circuit having a substrate region of semiconductor material of a first conductivity type, an epitaxial region of semiconductor material of a second conductivity type formed on the substrate region, a portion of the epitaxial region being isolated by an isolation region of semiconductor material of the first conductive type from the remainder thereof wherein an isolation pocket of the epitaxial region is defined, a combination capacitor and transistor structure, the improvement comprising: the isolated epitaxial pocket region having an outwardly planar facing surface and being the base region of the transistor, the substrate region lying under the isolated epitaxial pocket region being the collector region of the transistor; a first defined region of semiconductor material of the first conductivity type formed in the isolated epitaxial pocket region and having an outwardly facing surface coplanar with said outwardly facing surface of said isolated epitaxial pocket region, said first region being the emitter region of the transistor; a layer of dielectric material formed over said first region; a layer of metallic material formed over the dielectric material and said first region; and said layer of metallic material, in combination with said dielectric material and said first region forming a capacitor with said metallic material being a first plate of the capacitor and the active emitter region of the transistor being a second plate of the capacitor wherein the combined capacitor and transistor structure is realized by the capacitor being formed integrally with the active emitter region of the transistor.
Claim 3
Dependent Claim
38 words
The monolithic integrated circuit of claim 3 wherein said substrate region is of a P conductivity type, said first region is of said N- conductivity type, and said second and third regions are of said P+ conductivity type.
Claim 4
Dependent Claim
72 words
The monolithic integrated circuit of claim 1 including: a second defined region of semiconductor material of said first conductivity type formed in the isolated epitaxial pocket region in spaced relationship to said first region, said second region having an outwardly facing surface and forming with the substrate region and the isolated epitaxial pocket region a second transistor of the same conductivity type as the transistor of the combination transistor and capacitor structure.
References Cited (Backward Citations)
US3953875A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-13 | 1984-07-14 | 1985-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-13 | 1988-07-14 | 1989-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-13 | 1992-07-14 | 1993-01-13 | $7700.00 | Window Closed / Lapsed |