Low speed limiter unit for internal combustion engine ignition systems

Claim 2

In a solid state ignition system for a two-cycle engine, a low speed limit control means capable of producing an essentially concentrated, steep, step-like substantial advance of the ignition angle or timing with reducing engine speed, comprised of a rapidly responding electronic spark advance means and a speed sensing means connected to sense the engine speed and responsive below a preselected minimum engine speed to actuate said electronic spark advance means, and wherein said advance means and speed sensing means are constructed and arranged to change the ignition angle by approximately 9 degrees in a narrow speed range of less than plus and minus five percent of said preselected minimum engine speed.

Claim 3

In the ignition system of claim 1, wherein a switch means is included in the speed sensing means, said switch means being turned essentially wholly "on" and "off" in a narrow speed range including the minimum engine speed to turn the advance means on and off.

Claim 4

In the ignition system of claim 2 wherein an engine-driven alternator includes a stator winding having a speed-related output, the switch means including digital logic circuit elements coupled to the stator winding and generating a rapidly changing control signal at the preselected speed.

Claim 5

In the ignition system of claim 1 wherein the advance means has an asymmetrical rate of response and produces a relatively rapid advance output and a somewhat slower retard output in response to the speed sensing means.

Claim 6

In the ignition system of claim 3 wherein said advance means has an asymmetrical rate of response and produces a relatively rapid advance output and a somewhat slower retard output in response to the speed sensing means.

Claim 7

In the ignition system of claims 1, 2, 3, 4, or 5, wherein the spark advance means is limited to creating a substantial advance of the ignition angle at engine speeds substantially below maximum engine speed.

Claim 8

A low speed limiter unit for a solid state ignition system for a two-cycle internal combustion engine, containing an electronic advance means adapted to be driven fully on or fully off to automatically advance the spark angle and timing with a step-like characteristic of spark angle vs. engine speed, sensing means for sensing the engine speed and generating a plurality of pulses for each revolution of the engine, and speed switch means designed to receive and respond to said pulses and effectively control said electronic advance means to actuate said advance means in response to the frequency of said pulses dropping below that selected pulse frequency which is associated with the selected low limit engine speed, said speed sensing menas being provided with an input signal containing a plurality of voltage waves for each complete firing sequency of the engine, a shaping circuit being connected to receive said voltage waves and to generate for each individual voltage wave a generally rectangular pulse, said speed switch means including a restartable timing circuit means followed by a control switch means being connected to said shaping circuit for producing a first logic output condition above said selected pulse frequency and a second logic output condition below said selected pulse frequency, with said timing circuit means determining said first or second logic output conditions, respectively, of said switch means to drive said electronic advance means.

Claim 9

A low speed limiter unit for a solid state ignition system for a two-cycle internal combustion engine, containing an electronic advance means adapted to be driven fully on or fully off to automatically advance the spark angle and timing with a step-like characteristic of spark angle vs. engine speed, sensing means for sensing the engine speed and generating a plurality of pulses for each revolution of the engine, and speed switch means designed to receive and respond to said pulses and effectively control said electronic advance means to actuate said advance means in response to the frequency of said pulses dropping below that selected pulse frequency which is associated with the selected low limit engine speed, said speed sensing menas being provided with an input signal containing a plurality of voltage waves for each complete firing sequency of the engine, a shaping circuit being connected to receive said voltage waves and to generate for each individual voltage wave a generally rectangular pulse, said speed switch means including a restartable timing circuit means followed by a control switch means being connected to said shaping circuit for producing a first logic output condition above said selected pulse frequency and a second logic output condition below said selected pulse frequency, with said timing circuit means determining said first or second logic output conditions, respectively, of said switch means to drive said electronic advance means.

Claim 10

The low speed limiter unit of claim 7 including a response control network connected between said speed switch means and said advance means, said network including means to rapidly establish a control signal for actuating the advance means in response to a change to said second logic output and including means to less rapidly remove said control signal in response to the recovery from said second logic output to the first logic output.

Claim 11

The low speed limiter unit of claim 7 wherein said timing circuit means includes a pulse generator connected to said shaping circuit, a retriggerable monostable circuit having a trigger input connected to said pulse generator, and said control switch means includes a gated latch having main and complementary outputs, said latch having a first input connected to the pulse generator and a second input connected to the monostable circuit and having a main output signal essentially corresponding to the instantaneous state of the second input at the time that the first input drops below the gating threshold of the latch.

Claim 12

The low speed limiter unit of claim 7 wherein said timing circuit means includes first and second series connected retriggerable monostable circuits, and said control switch means includes a two input "OR" gate means connected to the monostable circuits.

Claim 13

The low speed limiter unit of claims 9 or 10 including a response control network connected between said control switch means and said advance means, said network including means to rapidly establish a control signal for actuating the advance means in response to said second logic output condition and including means to less rapidly remove said control signal in response to the recovery from said second logic output condition to the first logic output condition.

Claim 14

The low speed limiter unit of claim 11 applied to an ignition system having an ignition triggering reverse bias capacitor charged from the ignition systems trigger unit to maintain an essentially constant ignition angle with speed, wherein said advance means is a voltage controlled load able to drain charge from said bias capacitor having a control input connected to said response control network and an output connected to said bias capacitor to drain charge from said bias capacitor and thereby reduce the triggering reverse bias coltage and cause an electronic spark advance below said selected engine speed, and a current-limit means is included in said voltage-controlled load to limit the maximum load current.

Claim 15

The low speed limiter unit of claim 12 wherein said voltage-controlled load is a first high-gain transistor having its base-connected to the control voltage source and having negative current feedback provided by a current sensing resistor in series with the emitter of said first transistor, and said current-limit means is a second transistor having its input connected to said current sensing resistor and its output connected to reduce said control voltage source when the current in said current sensing resistor becomes excessive.

Claim 16

A low speed limiter unit for a solid state ignition system for a two-cycle internal combustion engine wherein the ignition system is driven from an alternator having a stator winding producing output voltage of a speed-related frequency, containing an electronic advance means adapted to be driven fully on or fully off to automatically advance the spark angle or timing with a step-like characteristic of spark angle vs. engine speed, sensing means for sensing the engine speed and generating a plurality of pulses for each revolution of the engine, and speed switch means designed to receive and respond to said pulses and effectively control said electronic advance means to actuate said advance means in response to the frequency of said pulses dropping below that selected pulse frequency which is associated with the selected low limit engine speed, said speed sensing means including a shaping circuit connected to said stator winding and producing a series of pulses having a frequency related to the frequency of said output voltage, said speed sensing means further includes a retriggerable timing unit having an input connected to said shaping circuit and having an output which remains at a first logic level when the frequency of said series of pulses is above a selected frequency and which switches between said first logic level and a second logic level when the frequency of said series of pulses is below said selected frequency, said speed switch means includes a gated latch means having inputs connected to said timing unit and to said shaping circuit to produce an essentially wholly off or wholly on output state in response to the inputs, said latch means being connected to actuate said advance means.

Claim 17

A low speed limiter unit for a solid state ignition system for a two-cycle internal combustion engine wherein the ignition system is driven from an alternator having a stator winding producing output voltage of a speed-related frequency, containing an electronic advance means adapted to be driven fully on or fully off to automatically advance the spark angle or timing with a step-like characteristic of spark angle vs. engine speed, sensing means for sensing the engine speed and generating a plurality of pulses for each revolution of the engine, and speed switch means designed to receive and respond to said pulses and effectively control said electronic advance means to actuate said advance means in response to the frequency of said pulses dropping below that selected pulse frequency which is associated with the selected low limit engine speed, said speed sensing means including a shaping circuit connected to said stator winding and producing a series of pulses having a frequency related to the frequency of said output voltage, said speed sensing means further includes a retriggerable timing unit having an input connected to said shaping circuit and having an output which remains at a first logic level when the frequency of said series of pulses is above a selected frequency and which switches between said first logic level and a second logic level when the frequency of said series of pulses is below said selected frequency, said speed switch means includes a gated latch means having inputs connected to said timing unit and to said shaping circuit to produce an essentially wholly off or wholly on output state in response to the inputs, said latch means being connected to actuate said advance means.

Claim 18

The low speed limiter unit of claim 14 wherein said timing unit includes a pulse generator connected to said shaping circuit to generate a control pulse for the combined purposes of triggering and latching, a retriggerable monostable circuit having a trigger input connected to said pulse generator, said retriggerable monostable circuit including first and second series connected logic gates with a delay means connected between the logic gates, and said gated latch includes a first input connected to the pulse generator and a second input connected to the monostable circuit and an output which produces a logic signal essentially corresponding to the logic signal existing at said second input when said control pulse terminates, said latch safely leaving data acquisition mode and entering data storage mode upon termination of said control pulse prior to reset of the second logic gate in delayed response to the termination of same said control pulse.

Claim 19

The low speed limiter unit of claim 15 including a response control network connected to said switch means and to said advance means, said network including means to rapidly establish a control signal for actuating the advance means in response to said second logic output condition or wholly on output state and including means to less rapidly remove said control signal in response to the change from said second logic output condition or wholly on state to said first logic output condition or wholly off output state.

Claim 20

In a capacitor discharge ignition system having an alternator for charging the discharge capacitor means and having a triggered thyristor means for discharging said discharge capacitor means and an ignition trigger signal source plus a reverse bias capacitor means connected to operate said thyristor means and establishing over the operating speed range of the engine an essentially constant ignition angle characteristic in the assumed absence of angular relocation of the ignition trigger signal source, a low speed limiter comprised of a signal shaping circuit connected to said alternator and producing a series of pulse signals for each complete firing sequency of the engine, the frequency of said pulse signals being directly related to the speed of the engine, said shaping circuit establishing a generally square wave pulse signal having a generally non-zero average value, a triggered solid state pulse source means for generating a short rectangular pulse signal of selected constant period for each said square wave pulse signal, a retriggerable timer including gated logic elements and time constant means connected to said triggered solid state means, a two input switch possessing memory with its first input connected to said triggered solid state means and its second input connected to said retriggerable timer, said two input switch being responsive to the logic level of the signal at its second input during the said short rectangular pulse generated by said triggered solid state means connected to its first input and operating solely on memory at all other times, said switch switching wholly on when the frequency of said pulses from said signal shaping circuit is below a selected frequency, and said switch switching wholly off when the frequency of said pulses from said signal shaping circuit is above said selected frequency, and a voltage controlled load conntected to said switch and to said reverse bias capacitor means and operable to reduce the voltage on the capacitor and thereby advance the ignition angle characteristic, said limiter therefore being active below a selected speed associated with said selected frequency, and inactive above said selected speed.

Claim 21

In a capacitor discharge ignition system having an alternator for charging the discharge capacitor means and having a triggered thyristor means for discharging said discharge capacitor means and an ignition trigger signal source plus a reverse bias capacitor means connected to operate said thyristor means and establishing over the operating speed range of the engine an essentially constant ignition angle characteristic in the assumed absence of angular relocation of the ignition trigger signal source, a low speed limiter comprised of a signal shaping circuit connected to said alternator and producing a series of pulse signals for each complete firing sequency of the engine, the frequency of said pulse signals being directly related to the speed of the engine, said shaping circuit establishing a generally square wave pulse signal having a generally non-zero average value, a triggered solid state pulse source means for generating a short rectangular pulse signal of selected constant period for each said square wave pulse signal, a retriggerable timer including gated logic elements and time constant means connected to said triggered solid state means, a two input switch possessing memory with its first input connected to said triggered solid state means and its second input connected to said retriggerable timer, said two input switch being responsive to the logic level of the signal at its second input during the said short rectangular pulse generated by said triggered solid state means connected to its first input and operating solely on memory at all other times, said switch switching wholly on when the frequency of said pulses from said signal shaping circuit is below a selected frequency, and said switch switching wholly off when the frequency of said pulses from said signal shaping circuit is above said selected frequency, and a voltage controlled load conntected to said switch and to said reverse bias capacitor means and operable to reduce the voltage on the capacitor and thereby advance the ignition angle characteristic, said limiter therefore being active below a selected speed associated with said selected frequency, and inactive above said selected speed.

Claim 22

In the ignition system of claim 17 wherein said low speed limiter responds by changing the ignition angle by approximately 9 degrees over a narrow speed range.

Claim 23

The ignition system of claim 18 wherein said advance is created in less than 5 percent of the preselected minimum speed.