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US4244056A Expired / Lapsed US ⏱️ 0.0 years remaining

Noise reduction circuit

Assignee: Faurecia Clarion Electronics Co Ltd
•
Filing: 1979-03-12
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Granted: 1981-01-06
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Expires: 1999-03-12
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Abstract

Abstract In an FM stereo-receiver, a noise reduction circuit includes a by-pass circuit connected between the output of an FM detector and an earth potential point, the time constant of which is controlled to continuously vary the frequency characteristic at a path from the FM detector to an MPX circuit, thereby greatly reducing a high frequency noise inherent therein.

Inventors

  • 👤 Masanori Hamada
  • 👤 Sueji Kawaguchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 19:56
CPC Classifications
H; H04; H04H; H04H40/00; H04H40/18; H04H40/27; H04H40/36; H04H40/45; H04H40/72; H03; H03G; H03G5/00; H03G5/16; H03G5/18; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/1646; H04B1/1661; H04B1/1669

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 122 words
A noise reduction circuit for an FM radio receiver, wherein said receiver includes at least IF signal generating means for producing an IF signal from a received incoming signal and FM detector means coupled to receive said IF signal, comprising a capacitor and a variable resistor means, said capacitor and said variable resistor means being connected in series between an output of said FM detector means and an earth potential point, and control means for continuously controlling the resistance of said variable resistor means in accordance with the level of said IF signal and thereby for continuously varying attenuation of a high frequency component of the incoming signal in response to the strength of the incoming signal to reduce noise contained therein.
Claim 2
Dependent Claim 122 words
A noise reduction circuit for an FM radio receiver, wherein said receiver includes at least IF signal generating means for producing an IF signal from a received incoming signal and FM detector means coupled to receive said IF signal, comprising a capacitor and a variable resistor means, said capacitor and said variable resistor means being connected in series between an output of said FM detector means and an earth potential point, and control means for continuously controlling the resistance of said variable resistor means in accordance with the level of said IF signal and thereby for continuously varying attenuation of a high frequency component of the incoming signal in response to the strength of the incoming signal to reduce noise contained therein.
Claim 3
Dependent Claim 35 words
A noise reduction circuit according to claim 1 wherein said variable resistor means includes an impedance varying transistor adapted to continuously vary its impedance in the active region thereof in response to said IF signal.
Claim 4
Dependent Claim 44 words
A noise reduction circuit according to claim 2 wherein said control means includes amplifier means for amplifying said IF signal, rectifier means for rectifying an output of said amplifier means and means for applying a rectified output of said rectifier means to the transistor.
Claim 5
Dependent Claim 54 words
A noise reduction circuit according to claim 3 which further includes a low frequency amplifying transistor for amplifying the output of said FM detector means to provide two low frequency amplified outputs in opposite phase to each other, said impedance varying transistor being coupled with said amplifying transistor to short-circuit said two amplified outputs.
Claim 6
Dependent Claim 28 words
A noise reduction circuit according to claim 1 wherein said variable resistor means includes photo-sensitive means the resistance of which continuously varies in response to the IF signal.
Claim 7
Dependent Claim 39 words
A noise reduction circuit according to claim 5 wherein said photo-sensitive means includes a light source for emitting light having intensity responsive to the IF signal and a photo-conductive element coupled to said light source to receive said light.
Claim 8
Dependent Claim 161 words
A noise reduction circuit for an FM radio receiver, wherein said receiver includes at least IF signal generating means for producing an IF signal from a received incoming signal and FM detector means coupled to receive said IF signal, comprising by-pass means connected between an output of said FM detector means and an earth potential point and control means for controlling a time constant of said by-pass means in accordance with the level of said IF signal whereby a noise signal contained in the incoming signal can be by-passed through said by-pass means, said by-pass means including a variable impedance transistor adapted to vary its impedance in response to said IF signal, said by-pass means further including a low frequency amplifying transistor for amplifying the output of said FM detector means to provide two low frequency amplified outputs in opposite phase to each other and said variable impedance transistor is coupled with said amplifying transistor to short-circuit said two amplified outputs.
Claim 9
Dependent Claim 161 words
A noise reduction circuit for an FM radio receiver, wherein said receiver includes at least IF signal generating means for producing an IF signal from a received incoming signal and FM detector means coupled to receive said IF signal, comprising by-pass means connected between an output of said FM detector means and an earth potential point and control means for controlling a time constant of said by-pass means in accordance with the level of said IF signal whereby a noise signal contained in the incoming signal can be by-passed through said by-pass means, said by-pass means including a variable impedance transistor adapted to vary its impedance in response to said IF signal, said by-pass means further including a low frequency amplifying transistor for amplifying the output of said FM detector means to provide two low frequency amplified outputs in opposite phase to each other and said variable impedance transistor is coupled with said amplifying transistor to short-circuit said two amplified outputs.

References Cited (Backward Citations)

US3912951A Cited
US4087641A Cited
US4063039A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1984-01-06 1984-07-07 1985-01-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1988-01-06 1988-07-07 1989-01-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1992-01-06 1992-07-07 1993-01-06 $7700.00 Window Closed / Lapsed

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