Receiver word alignment for digital transmission systems using a redundant ternary line code

Claim 3

An arrangement for aligning a digital transmission receiver to incoming redundant ternary line code signals comprising: first means coupled to said incoming signals to detect the presence of prohibited code words in different phases of said incoming signals and to produce a prohibited word signal, where the term "phases" is defined as the plurality of possible first digits in a ternary code word and a prohibited ternary code word is a redundant ternary code word not allocated to a binary equivalent; second means coupled to said first means to indicate when the accumulated disparity of said incoming signals, identified by timing control signals of said receiver, exceeds limits imposed by ternary code translating rules and to produce an alignment shift enable signal when said limits are exceeded; and third means coupled to said first and second means responsive to said prohibited word signal and said misalignment shift enable signal for selecting the phase having the lowest number of said prohibited code words if the rate at which said indications occur exceeds a predetermined level and to adjust said timing signals of said receiver for alignment thereof by said selected phase.

Claim 4

An arrangement for aligning a digital transmission receiver to incoming redundant ternary line code signals comprising: first means coupled to said incoming signals to detect the presence of prohibited code words in different phases of said incoming signals and to produce a prohibited word signal, where the term "phases" is defined as the plurality of possible first digits in a ternary code word and a prohibited ternary code word is a redundant ternary code word not allocated to a binary equivalent; second means coupled to said first means to indicate when the accumulated disparity of said incoming signals, identified by timing control signals of said receiver, exceeds limits imposed by ternary code translating rules and to produce an alignment shift enable signal when said limits are exceeded; and third means coupled to said first and second means responsive to said prohibited word signal and said misalignment shift enable signal for selecting the phase having the lowest number of said prohibited code words if the rate at which said indications occur exceeds a predetermined level and to adjust said timing signals of said receiver for alignment thereof by said selected phase.

Claim 5

An arrangement according to claim 2, wherein said first means includes a shift register coupled to said incoming signals having storage for 2 n signals, where n is the number of digits in a ternary line code word, only said ternary signals having positive and negative disparity being read into said register serially at a ternary line digit rate, and first logic means coupled to said register to detect sequences of n consecutive ternary digits having the same polarity and to generate said prohibited word signal whenever one of said sequences is detected, the contents of said register being transferred in parallel to said first logic means at said line digit rate.

Claim 6

An arrangement according to claim 3, wherein said second means includes second logic means coupled to said first logic means into which the contents of said register are transferred in parallel at said line digit rate, second logic means comparing the disparity of the last received group of n digits with the disparity of the immediately preceding received group of n signals at the termination of each received ternary code group, as defined by said timing control signals of said receiver and to generate violation pulses of the relative disparities of the last and immediately preceding received groups violate said ternary code translating rules, fourth means coupled to said second logic means for stretching said violation pulses to a predetermined duration, and fifth means coupled to said fourth means to divide the number of said stretched pulses by a fixed number to produce said alignment shift enable pulse.

Claim 7

An arrangement according to claim 4, wherein said third means includes n two input AND gates each having one input coupled to said first logic means responsive to said prohibited word signal, sixth means having n outputs each coupled to a different one of the other input of said AND gates to cyclically enable said AND gates at said line digit rate, n monostable multivibrators each coupled to an output of a different one of said AND gates for triggering thereof, each of said multivibrators having the same predetermined time constant, alignment logic means coupled to an output of each of said multivibrator to detect a condition when (n-1) of said multivibrators are triggered and one of said multivibrators is untriggered, coincident logic means coupled to said alignment logic means and said fifth means responsive to said line digit rate, said alignment shift enable signal and the output of said alignment logic means to select the output of said untriggered one of said multivibrators when there is coincidence between said line digit rate, said alignment shift enable signal and the output of said alignment logic means, and n NOR gates each coupled to the output of a different one of said multivibrators, the output of said coincidence logic means and a different one of said outputs of said sixth means.