Differential protection circuitry for electrical devices

Claim 2

Differential protection circuitry responsive to measured current pulses occurring upon external and internal faults of a protected device for emitting blocking and tripping signals, respectively, upon occurrence of an external and an internal fault of the protected device, the protection circuitry comprising: a stabilizing circuit including means for rectifying said measured current pulses, first and second level-sensing means each being responsive to a respective different polarity output of said rectifying means, and a stabilizing potentiometer connected in series with said first and second level sensing means; a differential circuit connected to the sliding terminal of said potentiometer for emitting tripping signals in conjunction with the operation of said stabilizing circuit; and blocking circuitry for blocking the emission of said tripping signals, and being responsive to the outputs of said first and second level-sensing means, said blocking circuitry being activated during a half cycle of said measured current pulses when overcurrent occurs in said stabilizing circuit before overcurrent occurs in said differential circuit and being reset when the currents through said two level-sensing means are below a predetermined level.

Claim 3

Differential protection circuitry as in claim 1 wherein said two level-sensing members and said differential circuit each comprise a relay having at least three relay contacts, said relay contacts being arranged in a three-by-three matrix with the contacts of each of said relays arranged in a respective column of said matrix and at least two rows of said matrix being connected in series to a tripping output terminal, the relay contacts of said differential relay being normally open in said first and second rows and closed in said third row, and the relay contacts of said first and second relays being normally alternately open and closed in the first two rows of said matrix and open in the third row thereof, and the rows of said matrix being connected to a power source.

Claim 4

Differential protection circuitry as in claim 2 wherein said blocking circuit includes a relay having a holding contact, and said differential relay includes an additional contact in said third row connected in series between said power source and said holding contact, said disconnecting relay including a normally closed contact in each of said first and second rows.

Claim 5

Differential protection circuitry as in claim 1 wherein said differential circuit includes a third level-sensing means and further comprising a first AND gate and an OR gate each having inputs connected to the output of each of the first, second and third level-sensing means, and a flip-flop circuit having respective set and reset inputs respectively connected to the output of said AND gate and said OR gate, a second AND gate having a first input connected to the output of said third level-sensing means and a second input connected to the output of said flip-flop circuit, the output of said second AND gate providing said tripping signals.

Claim 6

Differential protection circuitry responsive to measured current pulses occurring upon external and internal faults of a protected device for emitting blocking and tripping signals, respectively, upon occurrence of an external and an internal fault of the protected device, the protection circuitry comprising: a stabilizing circuit including first means for rectifying said measured current pulses, a level-sensing circuit connected across said first means for rectifying, a stabilizing potentiometer, and second means for rectifying interconnecting each terminal of said level-sensing circuit to a respective terminal of said stabilizing potentiometer whereby each terminal of said stabilizing potentiometer is responsive to a respective polarity output of said first rectifying means; a differential circuit connected to the sliding terminal of said stabilizing potentiometer for emitting tripping signals; and blocking circuitry for blocking the emission of said tripping signals, and being responsive to the output of said level-sensing circuit, said blocking circuitry being activated during a half cycle of said measured current pulses when overcurrent occurs in said stabilizing circuit before overcurrent occurs in said differential circuit, and being reset when the current through said level-sensing means is below a predetermined level.

Claim 7

Differential protection circuitry responsive to measured current pulses occurring upon external and internal faults of a protected device for emitting blocking and tripping signals, respectively, upon occurrence of an external and an internal fault of the protected device, the protection circuitry comprising: a stabilizing circuit including first means for rectifying said measured current pulses, a level-sensing circuit connected across said first means for rectifying, a stabilizing potentiometer, and second means for rectifying interconnecting each terminal of said level-sensing circuit to a respective terminal of said stabilizing potentiometer whereby each terminal of said stabilizing potentiometer is responsive to a respective polarity output of said first rectifying means; a differential circuit connected to the sliding terminal of said stabilizing potentiometer for emitting tripping signals; and blocking circuitry for blocking the emission of said tripping signals, and being responsive to the output of said level-sensing circuit, said blocking circuitry being activated during a half cycle of said measured current pulses when overcurrent occurs in said stabilizing circuit before overcurrent occurs in said differential circuit, and being reset when the current through said level-sensing means is below a predetermined level.

Claim 8

Differential protection circuitry as in claim 5 wherein said level-sensing circuit is a first relay, said differential circuit is a second relay, the relay contacts of said first relay and said second relay being connected in a two-by-two matrix with the contacts of each of said relays arranged in a respective column of said matrix and at least one row of said matrix being connected to a tripping output terminal, and the other row of said matrix being connected to said blocking circuit, said first row being connected to a power source, and the relay contacts of said first relay and said second relay being normally alternately open and closed in the first and second rows.

Claim 9

Differential protection circuitry as in claim 6 wherein said blocking circuit includes a relay having a holding contact and a contact connected in said first row in series with said tripping output terminal, and said second relay includes an additional contact connected in series with said holding contact and said power source and being normally open.

Claim 10

Differential protection circuitry for measuring current pulses resulting from external and internal faults of a protected device, comprising: current transformers for measuring the current in the protected device; a stabilizing circuit and a differential circuit connected to said current transformers for generating a tripping signal when the current in the differential circuit exceeds a predetermined value; each said stabilizing circuit and said differential circuit including level-sensing means for determining when the respective currents in the stabilizing and differential circuits exceed respective predetermined levels; blocking means connected to said level sensing means for blocking said tripping signal and being activated during a half cycle of the current when overcurrent occurs in the stabilizing circuit before the occurrence of overcurrent in the differential circuit, and said blocking devices being adapted to be reset when the currents through said level-sensing devices in the stabilizing and differential circuits fall below said predetermined levels.

Claim 11

Differential protection circuitry for measuring current pulses resulting from external and internal faults of a protected device, comprising: current transformers for measuring the current in the protected device; a stabilizing circuit and a differential circuit connected to said current transformers for generating a tripping signal when the current in the differential circuit exceeds a predetermined value; each said stabilizing circuit and said differential circuit including level-sensing means for determining when the respective currents in the stabilizing and differential circuits exceed respective predetermined levels; blocking means connected to said level sensing means for blocking said tripping signal and being activated during a half cycle of the current when overcurrent occurs in the stabilizing circuit before the occurrence of overcurrent in the differential circuit, and said blocking devices being adapted to be reset when the currents through said level-sensing devices in the stabilizing and differential circuits fall below said predetermined levels.

Claim 12

Protection circuitry as in claim 8 further comprising two separate conductors connected to said stabilizing circuit and said differential circuit and rectifying means interconnecting each said current measuring transformer and each of said two conductors, said stabilizing circuit including said level-sensing means in each of said two conductors.

Claim 13

Protection circuitry as in claim 8 further comprising two separate conductors connected to said stabilizing circuit and said differential circuit, and rectifying means interconnecting each said current measuring transformer and each of said two conductors, a resistance interconnecting said two conductors, said level-sensing means in said stabilizing circuit being connected between said two conductors.

Claim 14

Protection circuitry as in claim 8 wherein said blocking means includes bi-stable flip-flop means responsive to the output of said level-sensing means and a gating means responsive to the output of said bi-stable flip-flop means to be set in a blocking condition if overcurrent in said stabilizing current occurs before overcurrent in said differential circuit.