US4236197A
Expired / Lapsed
US
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Voltage regulation loop for inverter power supply
Assignee: Unisys Corp
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Filing: 1979-02-01
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Granted: 1980-11-25
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Expires: 1999-02-01
Abstract
Abstract A voltage regulation loop for the rejection of line frequency ripple of 0-180 Hz in an inverter power supply is disclosed. The loop includes an error amplifier (E), a pulse-width modulator (P), an inverter (I), a second summing node (N 2 ), an output filter (F), and a feedback loop back to a first summing node N 1 at the error amplifier. The novel pulse-width modulator is non-linearly operated to provide an improved rejection of the power supply's line frequency ripple and an improved stability.
Inventors
- 👤 Randolph D. W. Shelly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:38
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
224 words
In a voltage regulation loop for an inverter power supply including pulse-width modulator means, the input of which is a control signal v c that is generated from the power supply's output voltage v o and the output of which is a duty cycle signal v d that drives the power supply's inverter, the duty cycle D of said duty cycle signal v d of which is varied by a variation in the control voltage v c , an improved pulse-width modulator means, comprising: timing means for generating a timing signal of cycle time T and of duty cycle D 0 ; modulating means coupled to said timing means for generating a modulated output signal of cycle time T and of a variable duty cycle D+D 0 ; enabling means for generating alternative first and second enabling signals of cycle time T; first and second gating means; means coupling said signals of duty cycle D 0 and of duty cycle D+D 0 to said first and to said second gating means; means coupling said first enabling signal to said first gating means; means coupling said second enabling signal to said second gating means; said first and second enabling signals enabling said first and second gating means to generate respectively alternate pulse modulated output signals of cycle time T and a variable duty cycle D.
Claim 2
Dependent Claim
224 words
In a voltage regulation loop for an inverter power supply including pulse-width modulator means, the input of which is a control signal v c that is generated from the power supply's output voltage v o and the output of which is a duty cycle signal v d that drives the power supply's inverter, the duty cycle D of said duty cycle signal v d of which is varied by a variation in the control voltage v c , an improved pulse-width modulator means, comprising: timing means for generating a timing signal of cycle time T and of duty cycle D 0 ; modulating means coupled to said timing means for generating a modulated output signal of cycle time T and of a variable duty cycle D+D 0 ; enabling means for generating alternative first and second enabling signals of cycle time T; first and second gating means; means coupling said signals of duty cycle D 0 and of duty cycle D+D 0 to said first and to said second gating means; means coupling said first enabling signal to said first gating means; means coupling said second enabling signal to said second gating means; said first and second enabling signals enabling said first and second gating means to generate respectively alternate pulse modulated output signals of cycle time T and a variable duty cycle D.
Claim 3
Dependent Claim
257 words
In a voltage regulation loop for an inverter power supply including pulse-width modulator means, the input of which is a control signal v c that is generated from the power supply's output voltage v o and the output of which is a duty cycle signal v d that drives the power supply's inverter, the duty cycle D of said duty cycle signal v d of which is varied by a variation in the control voltage v c , an improved pulse-width modulator means, comprising: RC network means including a source of a variable amplitude control signal v c ; timing means for generating a timing signal of cycle time T and of duty cycle D 0 ; modulating means coupled to said RC network means and said timing means for generating a modulated output signal of cycle time T and of duty cycle D+D 0 that varies in duration in response to said variable amplitude control signal v c ; enabling means for generating alternative first and second enabling signals of cycle time T; first and second gating means; means coupling said signals of duty cycles D 0 and D+D 0 as first and second input signals to both said first and second gating means; means coupling said first enabling signal to said first gating means; means coupling said second enabling signal to said second gating means; said first and second enabling signals enabling said first and second gating means to generate respectively alternate pulse modulated output signals of cycle time T and of duty cycle D.
Claim 4
Dependent Claim
257 words
In a voltage regulation loop for an inverter power supply including pulse-width modulator means, the input of which is a control signal v c that is generated from the power supply's output voltage v o and the output of which is a duty cycle signal v d that drives the power supply's inverter, the duty cycle D of said duty cycle signal v d of which is varied by a variation in the control voltage v c , an improved pulse-width modulator means, comprising: RC network means including a source of a variable amplitude control signal v c ; timing means for generating a timing signal of cycle time T and of duty cycle D 0 ; modulating means coupled to said RC network means and said timing means for generating a modulated output signal of cycle time T and of duty cycle D+D 0 that varies in duration in response to said variable amplitude control signal v c ; enabling means for generating alternative first and second enabling signals of cycle time T; first and second gating means; means coupling said signals of duty cycles D 0 and D+D 0 as first and second input signals to both said first and second gating means; means coupling said first enabling signal to said first gating means; means coupling said second enabling signal to said second gating means; said first and second enabling signals enabling said first and second gating means to generate respectively alternate pulse modulated output signals of cycle time T and of duty cycle D.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-25 | 1984-05-26 | 1984-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-25 | 1988-05-26 | 1988-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-25 | 1992-05-26 | 1992-11-25 | $7700.00 | Window Closed / Lapsed |