Automatic AFT defeat circuit

Claim 2

An automatic AFT defeat circuit for a tuning voltage memory system having both AFT and FINE TUNING inputs, the defeat circuit comprising: a source of fine tuning voltage, a manual FINE TUNE switch having first and second sections, each with respective first, second and third terminals wherein the switch is so arranged and constructed that the first and second terminal of each section are connected when the FINE TUNE switch is activated and the second and third terminals are connected when the FINE TUNE switch is de-activated, and wherein: (1) the first terminal of the first section is connected to the FINE TUNING input, (2) the second and third terminals of the first section are connected to the source of FINE TUNING voltage, (3) the second terminal of the second section is connected to the AFT input, and (4) the third terminal of the second section is coupled to the output of an AFT detector.

Claim 3

An Automatic AFT Defeat circuit as defined in claim 1 further comprising loading means having an input coupled to the FINE TUNE switch and an output coupled to the AFT input for presenting the desired impedance at that input when the FINE TUNE switch is activated.

Claim 4

An Automatic AFT Defeat circuit as defined in claim 2 wherein the loading means comprises: a semiconductor switch; diode means coupled between the first terminal of the first section and the input of the semiconductor switch, and a resistance coupled between the output of the semiconductor switch is rendered conductive when the FINE TUNE switch is activated.

Claim 5

An Automatic AFT Defeat circuit as defined in claim 3 further comprising an AFT switch having two sections each with respective first, second and third terminals wherein the AFT switch is so arranged and constructed that the first and second terminals of each section are connected in the AFT OFF condition and the second and third terminals are connected in the AFT ON condition, and wherein: (1) the first terminal of the first section of the AFT switch is connected to the input of the semiconductor switch, (2) the second terminal of the first section of the AFT switch is connected to the source of fine tuning voltage, (3) the second terminal of the second section of the AFT switch is connected to the third terminal of the second section of the FINE TUNE switch, and (4) the third terminal of the second section of the AFT switch is coupled to the output of the AFT detector so that when the AFT switch is in the OFF condition the output of the AFT detector is disconnected from the FINE TUNE switch, and therefore from the tuning voltage control circuit, and the semiconductor switch is rendered conductive so that the desired impedance is presented at the AFT input.

Claim 6

An Automatic AFT Defeat circuit for a tuning voltage control system having AFT, Fine Tune Up and Fine Tune Down inputs, the defeat circuit comprising: a source of fine tuning voltage; a manual FINE TUNE switch having a first section comprising first, second, third and fourth terminals and having a second section comprising first and second terminals wherein the switch is so arranged and constructed that the first and second terminals of the first section are connected when the FINE TUNE switch is in the DOWN position, the third and fourth terminals of the first section are connected when the FINE TUNE switch is in the UP position and the first and second terminals of the second section are connected when the FINE TUNE switch is deactivated, and wherein: (1) the first terminal of the first section is connected to the Fine Tune Down input, (2) the second and third terminals of the first section are connected to the source of fine tuning voltage, (3) the fourth terminal of the first section is connected to the Fine Tune Up input, (4) the first terminal of the second section is connected to the AFT input, and (5) the second terminal of the second section is coupled to the output of an AFT detector.

Claim 7

An Automatic AFT Defeat circuit for a tuning voltage control system having AFT, Fine Tune Up and Fine Tune Down inputs, the defeat circuit comprising: a source of fine tuning voltage; a manual FINE TUNE switch having a first section comprising first, second, third and fourth terminals and having a second section comprising first and second terminals wherein the switch is so arranged and constructed that the first and second terminals of the first section are connected when the FINE TUNE switch is in the DOWN position, the third and fourth terminals of the first section are connected when the FINE TUNE switch is in the UP position and the first and second terminals of the second section are connected when the FINE TUNE switch is deactivated, and wherein: (1) the first terminal of the first section is connected to the Fine Tune Down input, (2) the second and third terminals of the first section are connected to the source of fine tuning voltage, (3) the fourth terminal of the first section is connected to the Fine Tune Up input, (4) the first terminal of the second section is connected to the AFT input, and (5) the second terminal of the second section is coupled to the output of an AFT detector.

Claim 8

An Automatic AFT defeat circuit as defined in claim 5 further comprising loading means having an input coupled to the FINE TUNE switch and an output coupled to the AFT input for presenting the desired impedance of that input whenever the FINE TUNE switch is activated.

Claim 9

An Automatic AFT defea circuit as defined in claim 6 wherein the loading means comprises: a semiconductor switch, first diode means coupled between the semiconductor switch and the Fine Tune Down input, second diode means coupled between the semiconductor switch and the Fine Tune Up input, and a resistance coupled between the semiconductor switch and the AFT input, whereby the semiconductor switch is rendered conductive whenever the FINE TUNE switch is activated.

Claim 10

In a tuning voltage memory system having both AFT and Fine Tuning inputs, the improvement comprising means for automatically defeating AFT operation during fine tuning conditions, said means including: a source of fine tuning voltage;

Claim 11

In a tuning voltage memory system having both AFT and Fine Tuning inputs, the improvement comprising means for automatically defeating AFT operation during fine tuning conditions, said means including: a source of fine tuning voltage;

Claim 12

a manual FINE TUNE switch having a first and second sections comprising respective first and second terminals, wherein the switch is so arranged and constructed that the first and second terminals of the first section are connected when the FINE TUNE switch is engaged and disconnected when the FINE TUNE switch is disengaed and the first and second terminals of the second section are disconnected when the FINE TUNE switch is engaged and connected when the FINE TUNE switch is disengaged and wherein; (1) the first terminal of the first section is connected to the Fine Tuning input, (2) the second terminal of the first section is connected to the source of fine tuning voltage, (3) the first terminal of the second section is connected to the AFT input, and (4) the second terminal of the second section is coupled to the output of an AFT detector.

Claim 13

a manual FINE TUNE switch having a first and second sections comprising respective first and second terminals, wherein the switch is so arranged and constructed that the first and second terminals of the first section are connected when the FINE TUNE switch is engaged and disconnected when the FINE TUNE switch is disengaed and the first and second terminals of the second section are disconnected when the FINE TUNE switch is engaged and connected when the FINE TUNE switch is disengaged and wherein; (1) the first terminal of the first section is connected to the Fine Tuning input, (2) the second terminal of the first section is connected to the source of fine tuning voltage, (3) the first terminal of the second section is connected to the AFT input, and (4) the second terminal of the second section is coupled to the output of an AFT detector.

Claim 14

An improvement as defined in claim 8 further comprising loading means having an input coupled to the FINE TUNE switch and an output coupled to the AFT input for presenting the desired impedance at the AFT input whenever the FINE TUNE switch is engaged.

Claim 15

The improvement as defined in either claim 8 or claim 9 further comprising: an AFT switch having first and second terminals, wherein the AFT switch is so arranged and constructed that the first and second terminals are connected in the AFT ON condition and disconnected in the AFT OFF condition and wherein: (1) the first terminal of the AFT switch is connected to the second terminal of the second section of the FINE TUNE switch and (2) the second terminal of the AFT switch is connected to the output of the AFT detector.

Claim 16

An improvement as defined in claim 9 further comprising an AFT switch having first and second sectons with respective first and second terminals, wherein the switch is so arranged and constructed that the first and second terminals of the first section are connected when the AFT switch is in the OFF condition and the first and second terminals of the second section are connected when the AFT switch is in the ON condition and wherein: (1) the first terminal of the first section of the AFT switch is connected to the loading means, (2) the second terminal of the second section of the AFT switch is connected to the source of fine tuning voltage, (3) the first terminal of the second section of the AFT switch is connected to the second terminal of the second section of the FINE TUNE switch and (4) the second terminal of the second section of the AFT switch is connected to the output of the AFT detector.

Claim 17

An improvement as defined in either claim 9 or claim 11 wherein the loading means comprises: a semiconductor switch, diode means connected between the FINE TUNE switch and the semiconductor switch, and a resistance connected between the semiconductor switch and the AFT input.