US4233674A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of configuring an integrated circuit
Assignee: Signetics Corp
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Filing: 1978-08-07
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Granted: 1980-11-11
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Expires: 1998-08-07
Abstract
Abstract In a method of configuring an integrated circuit provided in a semiconductor body having a surface and spaced semiconductor circuits formed in the body, intercoupling means are formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits. A static MOS random access memory having a 2,048 word capacity, with 9 bits/word and an 11 bit address is provided.
Inventors
- 👤 Lewis K. Russell
- 👤 David Kleitman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:54
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/418; H; H10; H10D; H10D84/00; H10D84/90; H10D84/903
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
277 words
A method of configuring an integrated circuit, comprising: (a) providing an array of unconnected semiconductor circuits spaced apart in a semiconductor body; (b) providing a pattern of conductive paths extending over a substantial portion of the length and breadth of a surface of said body, interlaced between said semiconductor circuits and spaced therefrom; (c) providing at least partly within said body adjacent to each of said semiconductor circuits and coupled between adjacent semiconductor circuits and adjacent conductive paths semiconductor switching means capable of being switched between high impedance and low impedance state; (d) testing each one of said semiconductor circuits to determine its operability; (e) recording the location of each of said semiconductor circuits and assigning an indicator to each location representing the operability or inoperability of each semiconductor circuit so located; (f) coupling at least some of said operable semiconductor circuits to said conductive paths by causing said semiconductor switching means selectively to assume a low impedance state adjacent to locations where the recording indicates an operable semiconductor circuit, and (g) decoupling said inoperable semiconductor circuits from said conductive paths by causing said semiconductor switching means to assume a high impedance state at locations where the recording indicates an inoperable semiconductor circuit, wherein the step in (e) includes mapping the cartesian coordinate location of said operable and inoperable circuits, producing a matrix of nodes located within groupings of adjacent circuits as represented by their cartesian coordinate location, summing the number of operable circuits in each grouping about a node, selecting those nodes which have the greater number of operable circuits adjacent thereto, and utilizing the results of said node selection to perform the step in (f).
Claim 2
Independent Claim
277 words
A method of configuring an integrated circuit, comprising: (a) providing an array of unconnected semiconductor circuits spaced apart in a semiconductor body; (b) providing a pattern of conductive paths extending over a substantial portion of the length and breadth of a surface of said body, interlaced between said semiconductor circuits and spaced therefrom; (c) providing at least partly within said body adjacent to each of said semiconductor circuits and coupled between adjacent semiconductor circuits and adjacent conductive paths semiconductor switching means capable of being switched between high impedance and low impedance state; (d) testing each one of said semiconductor circuits to determine its operability; (e) recording the location of each of said semiconductor circuits and assigning an indicator to each location representing the operability or inoperability of each semiconductor circuit so located; (f) coupling at least some of said operable semiconductor circuits to said conductive paths by causing said semiconductor switching means selectively to assume a low impedance state adjacent to locations where the recording indicates an operable semiconductor circuit, and (g) decoupling said inoperable semiconductor circuits from said conductive paths by causing said semiconductor switching means to assume a high impedance state at locations where the recording indicates an inoperable semiconductor circuit, wherein the step in (e) includes mapping the cartesian coordinate location of said operable and inoperable circuits, producing a matrix of nodes located within groupings of adjacent circuits as represented by their cartesian coordinate location, summing the number of operable circuits in each grouping about a node, selecting those nodes which have the greater number of operable circuits adjacent thereto, and utilizing the results of said node selection to perform the step in (f).
Claim 3
Dependent Claim
20 words
The invention according to claim 1 wherein said semiconductor circuits and said conductive paths are arranged in rows and columns.
Claim 4
Dependent Claim
38 words
The invention according to claim 2 and further including additional ones of said semiconductor switching means located peripherally of said array to provide connection between selected ones of said rows and columns of conductive paths to external circuitry.
Claim 5
Dependent Claim
64 words
The invention according to claim 1, wherein said semiconductor switching means includes a FET having a gate, and an avalanche charging element spaced from said FET and capable of avalanche breakdown in response to impressed voltage, said gate being coupled to said avalanche charging element to receive charge therefrom resulting from avalanche breakdown and thereupon causing said FET to assume a low impedance state.
Claim 6
Dependent Claim
26 words
The invention according to claim 4, wherein the low impedance state of said FET can be erased by applying radiant energy to said avalanche charging element.
Claim 7
Dependent Claim
34 words
The invention according to claim 1 and further including searching for those nodes which have no operable circuits adjacent thereto, and utilizing the results of said node search to perform the step in (g).
References Cited (Backward Citations)
US3813650A
Cited
US3940740A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-11 | 1984-05-12 | 1984-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-11 | 1988-05-12 | 1988-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-11 | 1992-05-12 | 1992-11-11 | $7700.00 | Window Closed / Lapsed |