Apparatus for determining the next address of a requested block in interlaced rotating memories

Claim 2

In a data processing system having a central processor unit (CPU) coupled to a memory storage subsystem which contains an interlaced serial rotational memory storage element of capacity 2 M cells whose cells may be accessed only at such point in time as they rotate to a position directly adjacent to a memory storage element access point and wherein the cells of said interlaced serial rotational memory storage element are accessed by said CPU as 2 M-N blocks of 2 N cells per block, where M is greater than N, and wherein each of said 2 M cells is identified with a different corresponding one of 2 M addresses and each of said 2 M addresses contains a block number identifying a one of said 2 M-N blocks and a word number identifying a one of said 2 N cells within the block identified by said block number, wherein said 2 M-N blocks are arranged such that said 2 M-N cells of each of said 2 M-N blocks are equally spaced about the entire rotation of said interlaced serial rotational memory storage element, and having a means responsively coupled to said interlaced serial rotational memory storage element for maintaining a one of said 2 M cells currently directly adjacent to said memory storage element access point, whereby said one of said 2 M addresses so maintained changes with the rotation of said memory storage element, and having a first transferring means responsively coupled to said memory storage subsystem and said CPU for transferring from said CPU to said memory storage subsystem an address corresponding to a one of the 2 N cells within a desired one of said 2 M-N blocks to be accessed by said CPU, and having a means responsively coupled to said maintaining means and said first transferring means for determining from said one of said 2 M addresses corresponding to the one of said 2 M cells currently directly adjacent to said memory storage element access point and from said one of said 2 M addresses corresponding to said one of said 2 N cells within said desired one of said 2 M-N blocks to be accessed by said CPU, an address corresponding to a one of the 2 N cells within said desired one of said 2 M-N blocks to next become adjacent to said memory storage element access point, and having a second transferring means responsively coupled to said determining means and said CPU for transferring said address determined by said determining means to said CPU to permit it to access said desired one of 2 M-N blocks from said determined address, said determining means comprising: first disassembly means responsively coupled to said first transferring means for disassembling said requested address transferred from said CPU into a requested block number identifying one of said 2 M-N blocks to be accessed and a requested word number identifying one of said 2 N storage cells within said requested block number; second disassembly means responsively coupled to said maintaining means for disassembling said address of said storage cell directly adjacent to said memory storage element access point into a memory block number identifying one of said 2 M-N blocks and a memory word number identifying one of said 2 N storage cells within said memory block number; a comparator responsively coupled to said first disassembly means and said second disassembly means which compares said requested block number with said memory block number; means responsively coupled to said comparator and said second disassembly means for selectively adding 1 to said memory word number if and only if said comparator indicates said requested block number is less than or equal to said memory block number; and means responsively coupled to said first disassembly means, said selective adding means, and said second transferring means for combining said requested block number with said memory word number as potentially modified by said selective adding means to produce said determined address to be transferred to said CPU.

Claim 3

In a data processing system according to claim 1: M=4; and N=2.

Claim 4

In a data processing system having a central processor unit (CPU) coupled to a memory storage subsystem which contains an interlaced serial rotational memory storage element of capacity 2 M cells whose cells may be accessed only at such point in time as they rotate to a position directly adjacent to a memory storage element access point and wherein the cells of said interlaced serial rotational memory storage element are accessed by said CPU as 2 M-N blocks of 2 N cells per block, where M is greater than N, and wherein each of said 2 M cells is identified with a different corresponding one of 2 M addresses and each of said 2 M addresses contains a block number identifying a one of said 2 M-N blocks and a word number identifying a one of said 2 N cells within the block identified by said block number, wherein said 2 M-N blocks are not equally spaced about the entire rotation of said interlaced serial rotational memory storage element, and having a means responsively coupled to said interlaced serial rotational memory storage element for maintaining a one of said 2 M addresses corresponding to the one of said 2 M cells currently directly adjacent to said memory storage element access point, whereby said one of said 2 M addresses so maintained changes with the rotation of said memory storage element, and having a first transferring means responsively coupled to said memory storage subsystem and said CPU for transferring from said CPU to said memory storage subsystem an address corresponding to a one of the 2 N cells within a desired one of said 2 M-N blocks to be accessed by said CPU, and having a means responsively coupled to said maintaining means and said first transferring means for determining from said one of said 2 M addresses corresponding to the one of said 2 M cells currently directly adjacent to said memory storage element access point and from said one of said 2 M addresses corresponding to said one of said 2 N cells within said desired one of said 2 M-N blocks to be accessed by said CPU, an address corresponding to a one of the 2 N cells within said desired one of said 2 M-N blocks to next become adjacent to said memory storage element access point, and having a second transferring means responsively coupled to said determining means and said CPU for transferring said address determined by said determining means to said CPU to permit it to access said desired one of 2 M-N blocks from said determined address, said determining means comprising: first disassembly means responsively coupled to said first transferring means for disassembling said requested address transferred from said CPU into a requested block number identifying one of said 2 M-N blocks to be accessed and a requested word number identifying one of said 2 N storage cells within said requested block number; second disassembly means responsively coupled to said maintaining means for disassembling said address of said storage cell directly adjacent to said memory storage element access point into a memory block number identifying one of said 2 M-N blocks and a memory word number identifying one of said 2 N storage cells within said memory block number; a comparator responsively coupled to said first disassembly means and said second disassembly means which compares said requested block number with said memory block number; means responsively coupled to said comparator and said second disassembly means for selectively adding 1 to said memory word number if and only if said comparator indicates said requested block number is less than or equal to said memory block number; means responsively coupled to said comparator and said second disassembly means for selectively setting to zero said memory word number if said comparator indicates that said one of 2 M-N blocks to be accessed is not located within that portion of said memory storage element presently adjacent said memory storage element access point; and means responsively coupled to said first disassembly means, said selective adding means, said selective setting means, and said second transferring means for combining said requested block number with said memory word number as potentially modified by said selective adding means to produce said determined address to be transferred to said CPU.

Claim 5

In a data processing system having a central processor unit (CPU) coupled to a memory storage subsystem which contains an interlaced serial rotational memory storage element of capacity 2 M cells whose cells may be accessed only at such point in time as they rotate to a position directly adjacent to a memory storage element access point and wherein the cells of said interlaced serial rotational memory storage element are accessed by said CPU as 2 M-N blocks of 2 N cells per block, where M is greater than N, and wherein each of said 2 M cells is identified with a different corresponding one of 2 M addresses and each of said 2 M addresses contains a block number identifying a one of said 2 M-N blocks and a word number identifying a one of said 2 N cells within the block identified by said block number, wherein said 2 M-N blocks are not equally spaced about the entire rotation of said interlaced serial rotational memory storage element, and having a means responsively coupled to said interlaced serial rotational memory storage element for maintaining a one of said 2 M addresses corresponding to the one of said 2 M cells currently directly adjacent to said memory storage element access point, whereby said one of said 2 M addresses so maintained changes with the rotation of said memory storage element, and having a first transferring means responsively coupled to said memory storage subsystem and said CPU for transferring from said CPU to said memory storage subsystem an address corresponding to a one of the 2 N cells within a desired one of said 2 M-N blocks to be accessed by said CPU, and having a means responsively coupled to said maintaining means and said first transferring means for determining from said one of said 2 M addresses corresponding to the one of said 2 M cells currently directly adjacent to said memory storage element access point and from said one of said 2 M addresses corresponding to said one of said 2 N cells within said desired one of said 2 M-N blocks to be accessed by said CPU, an address corresponding to a one of the 2 N cells within said desired one of said 2 M-N blocks to next become adjacent to said memory storage element access point, and having a second transferring means responsively coupled to said determining means and said CPU for transferring said address determined by said determining means to said CPU to permit it to access said desired one of 2 M-N blocks from said determined address, said determining means comprising: first disassembly means responsively coupled to said first transferring means for disassembling said requested address transferred from said CPU into a requested block number identifying one of said 2 M-N blocks to be accessed and a requested word number identifying one of said 2 N storage cells within said requested block number; second disassembly means responsively coupled to said maintaining means for disassembling said address of said storage cell directly adjacent to said memory storage element access point into a memory block number identifying one of said 2 M-N blocks and a memory word number identifying one of said 2 N storage cells within said memory block number; a comparator responsively coupled to said first disassembly means and said second disassembly means which compares said requested block number with said memory block number; means responsively coupled to said comparator and said second disassembly means for selectively adding 1 to said memory word number if and only if said comparator indicates said requested block number is less than or equal to said memory block number; means responsively coupled to said comparator and said second disassembly means for selectively setting to zero said memory word number if said comparator indicates that said one of 2 M-N blocks to be accessed is not located within that portion of said memory storage element presently adjacent said memory storage element access point; and means responsively coupled to said first disassembly means, said selective adding means, said selective setting means, and said second transferring means for combining said requested block number with said memory word number as potentially modified by said selective adding means to produce said determined address to be transferred to said CPU.

Claim 6

In a data processing system according to claim 3: M=4; and N=2.