US4231024A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for a digital arithmetic processing apparatus
Assignee: Toshiba Corp
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Filing: 1976-11-12
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Granted: 1980-10-28
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Expires: 1996-11-12
Abstract
Abstract A data-entry device for digital arithmetic processing apparatus which has a semiconductor integrated circuit provided with a plurality of terminals, key signal control leads, the one side ends of which are connected to respective ones of the plurality of terminals, and a keyboard device having terminals connected to the other side ends of the key signal control leads. The semiconductor integrated circuit includes a plurality of FET's with respective drains connected to respective terminals of the semiconductor integrated circuit with sources grounded and with gates applied with key signal-generating pulses in different timings. The semiconductor integrated circuit further includes at least one timing inhibition circuit which has a first input terminal connected to at least one of the terminals of the semiconductor integrated circuit and has a second input terminal supplied with a key signal-generating pulse. There is also provided at least one inverter connected to one of the plurality of terminals of the semiconductor integrated circuit. The keyboard device is provided with a plurality of key switches connected between the respective keyboard terminals. The data entry device operates such that upon receipt of a key signal-generating pulse the inhibition circuit inhibits a key signal from the corresponding key switch.
Inventors
- 👤 Eiichi Munetsugu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:17
CPC Classifications
H; H03; H03M; H03M11/00; H03M11/20
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
373 words
A data entry device comprising: a keyboard device having a first keyboard terminal, at least one second keyboard terminal, and a third keyboard terminal; a plurality of keyboard switch means for selectively interconnecting said first, second, and third keyboard terminals; a semiconductor integrated circuit for cyclically providing at least first and second keyboard sampling pulses at different times with respect to each other; a first terminal pin; at least one second terminal pin; a third terminal pin; a first gate circuit through which said first terminal pin receives said first keyboard sampling pulses; a second gate circuit through which said at least one second terminal pin receives said second keyboard sampling pulses; an output-only lead connecting said first terminal pin and said first keyboard terminal for transmitting said first keyboard sampling pulses from said first terminal pin to said first keyboard terminal; an output/input lead connecting said at least one second terminal pin with said at least one second keyboard terminal, said output/input lead (1) for transmitting a said first keyboard sampling pulse from said at least one second keyboard terminal to said at least one second terminal pin when a said keyboard switch means is selected to interconnect said first keyboard terminal to said at least one second keyboard terminal during the occurrence of a said first keyboard sampling pulse, and (2) for transmitting said second keyboard sampling pulses from said at least one second terminal pin to said at least one second keyboard terminal; at least one timing-inhibition circuit having an input terminal connected to a said at least one second terminal pin for generating a key select signal only in response to said transmission of a said first keyboard sampling pulse to said at least one second terminal pin; and an input-only lead connecting said third keyboard terminal to said third terminal pin for transmitting said first keyboard sampling pulses to said third terminal pin when a said keyboard switch means is selected to interconnect said first keyboard terminal to said third keyboard terminal, and for transmitting said second keyboard sampling pulses to said third terminal pin when a said keyboard switch means is selected to interconnect a said at least one second keyboard terminal to said third keyboard terminal.
Claim 2
Dependent Claim
373 words
A data entry device comprising: a keyboard device having a first keyboard terminal, at least one second keyboard terminal, and a third keyboard terminal; a plurality of keyboard switch means for selectively interconnecting said first, second, and third keyboard terminals; a semiconductor integrated circuit for cyclically providing at least first and second keyboard sampling pulses at different times with respect to each other; a first terminal pin; at least one second terminal pin; a third terminal pin; a first gate circuit through which said first terminal pin receives said first keyboard sampling pulses; a second gate circuit through which said at least one second terminal pin receives said second keyboard sampling pulses; an output-only lead connecting said first terminal pin and said first keyboard terminal for transmitting said first keyboard sampling pulses from said first terminal pin to said first keyboard terminal; an output/input lead connecting said at least one second terminal pin with said at least one second keyboard terminal, said output/input lead (1) for transmitting a said first keyboard sampling pulse from said at least one second keyboard terminal to said at least one second terminal pin when a said keyboard switch means is selected to interconnect said first keyboard terminal to said at least one second keyboard terminal during the occurrence of a said first keyboard sampling pulse, and (2) for transmitting said second keyboard sampling pulses from said at least one second terminal pin to said at least one second keyboard terminal; at least one timing-inhibition circuit having an input terminal connected to a said at least one second terminal pin for generating a key select signal only in response to said transmission of a said first keyboard sampling pulse to said at least one second terminal pin; and an input-only lead connecting said third keyboard terminal to said third terminal pin for transmitting said first keyboard sampling pulses to said third terminal pin when a said keyboard switch means is selected to interconnect said first keyboard terminal to said third keyboard terminal, and for transmitting said second keyboard sampling pulses to said third terminal pin when a said keyboard switch means is selected to interconnect a said at least one second keyboard terminal to said third keyboard terminal.
Claim 3
Dependent Claim
65 words
A data-entry device according to claim 1, wherein the timing-inhibition circuit comprises an inverter having an input terminal, connected to said at least one second terminal pin, and an output terminal, and an AND circuit having a first input connected to the output terminal of said inverter and a second input supplied with either said first keyboard sampling pulses or said second keyboard sampling pulses.
Claim 4
Dependent Claim
95 words
A data-entry device according to claim 1, wherein the timing-inhibition circuit comprises an inverter having an input terminal connected to a said at least one second terminal pin and an output terminal; an AND circuit having a first input terminal connected to the output terminal of said inverter and a second input terminal; and an OR circuit having an output terminal connected to said second input terminal of said AND circuit and a first input terminal for receiving said first keyboard sampling pulses and a second input terminal for receiving said second keyboard sampling pulses.
Claim 5
Dependent Claim
88 words
A data entry device according to claim 1, wherein the second gate circuit comprises a complementary MOS circuit including at least one MOS transistor having a drain connected to said at least one second terminal pin, a grounded source, and a gate supplied with said second keyboard sampling pulses, whereby said MOS transistor receives said second keyboard sampling pulses and prevents a key select signal from being generated by said timing-inhibition circuit upon receipt of said second keyboard sampling pulses through said at least one second terminal pin.
Claim 6
Dependent Claim
17 words
A data entry device according to claim 1, wherein the timing inhibition circuit comprises a NOR circuit.
Claim 7
Dependent Claim
105 words
A data entry device according to claim 1, wherein the second gate circuit comprises at least one complementary MOS circuit having an output terminal connected to said at least one second terminal pin and an input terminal for receiving said second keyboard sampling pulses, said complementary MOS circuit including a P-channel MOS transistor and an N-channel MOS transistor connected in series between power supply terminals, whereby said complementary MOS circuit receives said second keyboard sampling pulses and prevents a key select signal from being generated by said timing-inhibition circuit upon receipt of said second keyboard sampling pulses from said at least one second terminal pin.
Claim 8
Dependent Claim
42 words
A data-entry device according to claim 6, wherein the N-channel MOS transistor and P-channel MOS transistor each have a mutual conductance and wherein the mutual conductance of the N-channel MOS transistor is smaller than the mutual conductance of the P-channel MOS transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-28 | 1984-04-28 | 1984-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-28 | 1988-04-28 | 1988-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-28 | 1992-04-28 | 1992-10-28 | $7700.00 | Window Closed / Lapsed |