US4229701A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse order recognition circuit
Assignee: KENT COUNTY COUNCIL
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Filing: 1978-04-27
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Granted: 1980-10-21
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Expires: 1998-04-27
Abstract
Abstract A circuit which has two inputs at which respective ones of two time-displaced pulses may be received. The circuit also has an output at which a signal is produced if the pulses arrive in one order but not if they arrive in the opposite order. The circuit may have a second output at which a signal is produced if they arrive in said opposite order but not if they arrive in said one order. If spaced apart movement sensors are used to provide the two input signals, the circuit having two outputs indicates in which of two directions an object such as a vehicle passes the sensors. If only a single output is employed the circuit indicates each object passing in one direction but ignores objects passing in the opposite direction. Further applications of the circuit are disclosed.
Inventors
- 👤 Malcolm S. Bourner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:23
CPC Classifications
G; G01; G01P; G01P3/00; G01P3/64; G01P3/66; G01P13/00; G01P13/02; G01P13/04; H; H03; H03K; H03K5/00; H03K5/22; H03K5/26
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
161 words
A pulse order recognition circuit having a quiescent condition and comprising first and second inputs for receiving when the circuit is in said quiescent condition respective ones of two electrical pulses displaced relative to each other in time, at least one output, means for providing at said output an output signal in response to the earlier of said pulses being received at said first input and the later of said pulses being received at said second input, means for preventing said output signal from being provided at said output in response to the earlier of said pulses being received at said second input and the later of said pulses being received at said first input, said providing means and said preventing means being adapted to so operate irrespective of whether the two pulses overlap in time, or not, and means responsive to said later pulse for resetting the circuit to said quiescent condition ready to receive a further two said pulses.
Claim 2
Dependent Claim
161 words
A pulse order recognition circuit having a quiescent condition and comprising first and second inputs for receiving when the circuit is in said quiescent condition respective ones of two electrical pulses displaced relative to each other in time, at least one output, means for providing at said output an output signal in response to the earlier of said pulses being received at said first input and the later of said pulses being received at said second input, means for preventing said output signal from being provided at said output in response to the earlier of said pulses being received at said second input and the later of said pulses being received at said first input, said providing means and said preventing means being adapted to so operate irrespective of whether the two pulses overlap in time, or not, and means responsive to said later pulse for resetting the circuit to said quiescent condition ready to receive a further two said pulses.
Claim 3
Dependent Claim
43 words
A circuit as claimed in claim 1, wherein said first input and said output are linked by a signal transmission channel and means is provided for blocking said channel in response to the earlier of said pulses being received at said second input.
Claim 4
Dependent Claim
86 words
A circuit as claimed in claim 1, having a second output, means for providing at said second output an output signal in response to the earlier of said pulses being received at said second input and the later of said pulses being received at said first input, and means for preventing said output signal being provided at said second input in response to the earlier of said pulses being received at said first input and the later of said pulses being received at said second input.
Claim 5
Dependent Claim
81 words
A circuit as claimed in claim 3, wherein said first input and said output are linked by a signal transmission channel and means is provided for blocking said channel in response to the earlier of said pulses being received at said second input, said second input and said second output are linked by a second signal transmission channel and means is provided for blocking said second channel in response to the earlier of said pulses being received at said first input.
Claim 6
Dependent Claim
26 words
A circuit as claimed in claim 2, wherein said re-setting means is responsive to the later pulse to re-set said blocking means to an unblocked condition.
Claim 7
Dependent Claim
36 words
A circuit as claimed in claim 4, wherein said re-setting means is responsive to the later pulse to re-set to an unblocking condition either of the blocking means which has been set to a blocking condition.
Claim 8
Dependent Claim
53 words
A circuit as claimed in claim 6, comprising means for eliminating a portion of a pulse in one said channel which overlaps a pulse in the other said channel thereby separating, in time, the pulses in the channels and providing a later pulse distinct from the earlier pulse for re-setting said blocking means.
Claim 9
Dependent Claim
25 words
A circuit as claimed in claim 2, comprising further re-setting means for re-setting said blocking means to an unblocked condition after a predetermined delay period.
Claim 10
Dependent Claim
25 words
A circuit as claimed in claim 6, comprising further re-setting means for re-setting said blocking means to an unblocked condition after a predetermined delay period.
Claim 11
Dependent Claim
91 words
In combination, a pulse order recognition circuit as claimed in claim 1, two sensors each adapted to produce a pulse in response to movement of a body past the sensor, the sensors being positioned to respond in succession to passage of a body along a path and thereby to produce two pulses in succession, and means coupling the sensors respectively to the first and second inputs of the pulse order recognition circuit, whereby to distinguish movement of said body in one direction along said path from movement in an opposite direction.
Claim 12
Dependent Claim
103 words
In combination, a pulse order recognition circuit as claimed in claim 3, two sensors each adapted to produce a pulse in response to movement of a body past the sensor, the sensors being positioned to respond in succession to passage of a body along a path and thereby to produce two pulses in succession, and means coupling the sensors respectively to the first and second inputs of the pulse order recognition circuit, whereby to provide at one output output signals indicative of a body travelling in one direction, and at the other output signals indicative of a body travelling in the opposite direction.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-21 | 1984-04-21 | 1984-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-21 | 1988-04-21 | 1988-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-21 | 1992-04-21 | 1992-10-21 | $7700.00 | Window Closed / Lapsed |