Interface unit for data exchange between a central processor and a peripheral unit in TDM telecommunication system

Claim 2

In a TDM telecommunication system wherein a central processor dialogues with a plurality of peripheral units each having a multiplicity of loads activable in time slots individually assigned thereto in a recurrent scanning cycle, the combination therewith of an interface unit interposed between said processor and an associated peripheral unit, said interface unit comprising: a receiving section with first input means connected to said processor and first output means connected to the associated peripheral unit; a transmitting section with second input means connected to the associated peripheral unit and second output means connected to said processor; a series/parallel register in said receiving section having a series input connected to said first input means for the temporary storage of incoming messages from said processor; a parallel/series register in said transmitting section with parallel inputs connected to said second input means for the temporary storage of return messages from the associated peripheral unit; memory means in said receiving section having a multiplicity of cells connected to said first output means, said cells being respectively allocated to said loads and identified by address codes corresponding to the time slots assigned thereto; timer-operated first control means in said receiving section responsive to a signal from said series/parallel register for directing the writing of an operative code of an incoming message, destined for a load of the associated peripheral unit identified by an accompanying address code, in the allocated cell of said memory means during one part of a time slot and for commanding the readout to said first output means, during another part of a time slot, of the contents of the cell allocated to the load which is activable in the immediately following time slot; and second control means in said transmitting section responsive to a signal from said parallel/series register for routing return messages from the associated peripheral unit to said second output means.

Claim 3

The combination defined in claim 1 wherein said series/parallel register includes decoding means for detecting a recycle message to be serially relayed to said parallel/series register for retransmission to said processor.

Claim 4

The combination defined in claim 1 wherein the incoming messages include signalization messages and supervisory messages distinguished by different digital labels, only said signalization messages bearing an address code identifying a cell in said memory means, said first control means including first instruction means for routing said supervisory messages from said receiving section to said transmitting section, said second control means including second instruction means for retransmitting responses to said supervisory messages to said processor by way of said second output means.

Claim 5

In a TDM telecommunication system wherein a central processor dialogues with a plurality of peripheral units each having a multiplicity of loads activable in time slots individually assigned thereto in a recurrent scanning cycle, the combination therewith of an interface unit interposed between said processor and an associated peripheral unit, said interface unit comprising: a receiving section with first input means connected to said processor and first output means connected to the associated peripheral unit; a transmitting section with second input means connected to the associated peripheral unit and second output means connected to said processor; first register means in said receiving section connected to said first input means for the temporary storage of incoming messages from said processor, said incoming messages including signalization messages and supervisory messages distinguished by different digital labels; second register means in said transmitting section connected to said second input means for the temporary storage of return messages from the associated peripheral unit; memory means in said receiving section having a multiplicity of cells connected to said first output means, said cells being respectively allocated to said loads and identified by address codes of said signalization messages corresponding to the time slots assigned thereto; timer-operated first control means in said receiving section responsive to a signal from said first register means for directing the writing of an operative code of an incoming message, destined for a load of the associated peripheral unit identified by an accompanying address code, in the allocated cell of said memory means during one part of a time slot and for commanding the readout to said first output means, during another part of a time slot, of the contents of the cell allocated to the load which is activable in the immediately following time slot, said first control means including first instruction means for routing said supervisory messages from said receiving section to said transmitting section; and second control means in said transmitting section responsive to a signal from said second register means for routing return messages from the associated peripheral unit to said second output means, said second control means including second instruction means for retransmitting responses to said supervisory messages from said interface unit to said processor by way of said second output means.

Claim 6

In a TDM telecommunication system wherein a central processor dialogues with a plurality of peripheral units each having a multiplicity of loads activable in time slots individually assigned thereto in a recurrent scanning cycle, the combination therewith of an interface unit interposed between said processor and an associated peripheral unit, said interface unit comprising: a receiving section with first input means connected to said processor and first output means connected to the associated peripheral unit; a transmitting section with second input means connected to the associated peripheral unit and second output means connected to said processor; first register means in said receiving section connected to said first input means for the temporary storage of incoming messages from said processor, said incoming messages including signalization messages and supervisory messages distinguished by different digital labels; second register means in said transmitting section connected to said second input means for the temporary storage of return messages from the associated peripheral unit; memory means in said receiving section having a multiplicity of cells connected to said first output means, said cells being respectively allocated to said loads and identified by address codes of said signalization messages corresponding to the time slots assigned thereto; timer-operated first control means in said receiving section responsive to a signal from said first register means for directing the writing of an operative code of an incoming message, destined for a load of the associated peripheral unit identified by an accompanying address code, in the allocated cell of said memory means during one part of a time slot and for commanding the readout to said first output means, during another part of a time slot, of the contents of the cell allocated to the load which is activable in the immediately following time slot, said first control means including first instruction means for routing said supervisory messages from said receiving section to said transmitting section; and second control means in said transmitting section responsive to a signal from said second register means for routing return messages from the associated peripheral unit to said second output means, said second control means including second instruction means for retransmitting responses to said supervisory messages from said interface unit to said processor by way of said second output means.

Claim 7

The combination defined in claim 4 wherein said instruction means are microprogram stores.

Claim 8

The combination defined in claim 5 wherein said first control means further includes a source of microprogram addresses provided with timer-actuated switchover means for extracting from the microprogram store thereof an invariable reading instruction in said other part of a time slot.

Claim 9

The combination defined in claim 6 wherein said switchover means is responsive to a cancellation message from the associated peripheral unit for extracting from the microprogram store thereof a message-deleting instruction in said one part of a time slot.

Claim 10

The combination defined in claim 6 wherein said source of microprogram addresses comprises a comparator with input connections to an output of said first register means and to an output of the microprogram store of said first control means, an address register, a feedback line extending from the last-mentioned output, an incrementer connected to an output of said address register, and a multiplexer controlled by said comparator for alternatively connecting said feedback line and said incrementer to an input of said address register.

Claim 11

The combination defined in claim 8 wherein said switchover means is inserted between said address register and the microprogram store of said first control means.

Claim 12

The combination defined in claim 4 wherein said incoming messages further include universal messages intended for all said loads, said receiving section further comprising a buffer register inserted between said first register means and said first output means in parallel with said memory means for routing an incoming universal message directly to the associated peripheral unit.