CRT Display apparatus with changeable cursor indicia

Claim 1

A CRT display apparatus comprising: a refresh memory for storing display data for one frame of an image in the form of coded data; input/output control means coupled to the refresh memory for controlling the input and output of information to and from said refresh memory; video control means coupled to the refresh memory for converting the display data read from said refresh memory into a video signal; a CRT display device coupled to the video control means for converting said video signal into a visible image; timing control means coupled to the refresh memory, the video control means and the CRT display device for generating a plurality of synchronizing signals for a raster scanning of said CRT display device and for generating a display address for reading said refresh memory corresponding to said raster scanning; and cursor display control means coupled to the timing control means, the video control means, and the input/output means for generating a cursor display signal, wherein said cursor display control means comprises: a cursor start address register coupled to said input/output control means for producing a programmed cursor start address; a cursor end address register coupled to said input/output control means for producing a programmed cursor end address; a cursor register coupled to said input/output control means for generating a cursor display address; a cursor coincidence detector coupled to said timing control means and said cursor register for producing a cursor coincidence signal representative of coincidence of said display address with said cursor display address; a first coincidence detector coupled to said cursor start address register and said timing control means for producing a first signal pulse representative of coincidence of said programmed cursor start address and said display address; a second coincidence detector coupled to said cursor end address register and said timing control means for producing a second signal pulse representative of coincidence of said programmed cursor end address and said display address; a first differentiating circuit coupled to said first coincidence detector for producing a third signal pulse representative of a leading edge of said first signal pulse; a second differentiating circuit coupled to said second coincidence detector for producing a fourth signal pulse representative of a trailing edge of said second signal pulse; a flip-flop set by said third signal pulse and reset by said fourth signal pulse for producing the cursor display signal; and a gate for passing said cursor display signal to said video control means only at a period during which said cursor coincidence detector produces the cursor coincidence signal.