US4224534A
Expired / Lapsed
US
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Tri-state signal conditioning method and circuit
Assignee: HP Inc
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Filing: 1977-08-17
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Granted: 1980-09-23
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Expires: 1997-08-17
Abstract
Abstract A method and apparatus for converting a tri-state logic signal into a two-state logic signal accurately and repeatably for purposes of signal measurement. In particular, the method and apparatus deal with how the third, or high impedance state is translated into a high or a low state. This is accomplished by including a resistor of a selected value to form a voltage divider with the resistance of the path through which the stray capacitance of the circuit under test charges during these intervals. Thus, the level of the final voltage charge is limited to a selected voltage that is intermediate the high and low state threshold voltages of that circuit. The initially conditioned signal, now a true tri-stage signal, is next applied to two threshold detectors, whose outputs in turn are applied to a state machine. This combination generates a repeatable two-state signal by identifying each occurrence of the third state as the last previous high or low state, i.e., the output of the conditioning circuit does not switch to the other state until both thresholds have been crossed by the signal in either direction, at the clock time. The resultant signal from the conditioning circuit has only two predictable and repeatable states, the low and the high states.
Inventors
- 👤 Gary B. Gordon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:50
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0002
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
208 words
A method of generating a repeatable binary signal from a tri-state signal to characterize said tri-state signal for testing, both signals having the same preselected clock rate, and said tri-state signal being the output signal of a logic circuit wherein the output signal has a high state region, a low state region, and a floating region, said high and low state regions being defined by the logic circuit when its output stage is clamped to a voltage level that is greater than or less than a first and a second signal threshold level, respectively, and said floating region occurring when the output stage of the logic circuit is unclamped to any voltage level, the method comprising the steps of: a. limiting the variation of the tri-state signal in the floating regions to a single transition of one of said first and second signal threshold levels; b. sampling the limited tri-state signal of step a. in relation to the preselected clock rate; and c. identifying the sampled, limited high and low state regions of the tri-state signal as high and low states, respectively, and identifying its regions limited in step a. as being in the same state as the last previous one of the high and low state regions.
Claim 2
Independent Claim
208 words
A method of generating a repeatable binary signal from a tri-state signal to characterize said tri-state signal for testing, both signals having the same preselected clock rate, and said tri-state signal being the output signal of a logic circuit wherein the output signal has a high state region, a low state region, and a floating region, said high and low state regions being defined by the logic circuit when its output stage is clamped to a voltage level that is greater than or less than a first and a second signal threshold level, respectively, and said floating region occurring when the output stage of the logic circuit is unclamped to any voltage level, the method comprising the steps of: a. limiting the variation of the tri-state signal in the floating regions to a single transition of one of said first and second signal threshold levels; b. sampling the limited tri-state signal of step a. in relation to the preselected clock rate; and c. identifying the sampled, limited high and low state regions of the tri-state signal as high and low states, respectively, and identifying its regions limited in step a. as being in the same state as the last previous one of the high and low state regions.
Claim 3
Dependent Claim
36 words
A method of generating a repeatable binary signal as in claim 1 wherein step a. includes pulling the tri-state signal in the floating regions toward a signal level intermediate said first and second signal threshold levels.
Claim 4
Dependent Claim
174 words
A method of generating a repeatable binary signal as in claim 1 wherein step c. includes: d. storing the state level of the last previous one of the high and low state regions of the tri-state signal as limited in step a.; e. comparing the signal level of the tri-state signal as limited in step a. in each of its regions to said first and second threshold signal levels; and f. generating a signal in response to the preselected clock rate, said signal having a high state region in response to both of said first and second signal threshold levels being exceeded in the signal comparing step e., a low state region in response to neither of said first and second signal threshold levels being exceeded in the signal comparing step e., and having a state region with the same state level as the state level retained in the storing step d. when the signal level of the tri-state signal limited as in step a. is intermediate said first and second signal threshold levels.
Claim 5
Independent Claim
217 words
An apparatus for generating a repeatable binary signal from a tri-state signal to characterize said tri-state signal for testing, both signals having the same preselected clock rate, and said tri-state signal being the output signal of a logic circuit wherein the output signal has a high state region defined as that region wherein the output stage of the logic circuit is clamped to a voltage level above a first signal threshold level, a low state region defined as that region when the output stage of the logic circuit is clamped to a voltage level below a second signal threshold level, and a floating region in those intervals when the output stage of the logic circuit is unclamped to any voltage level, said apparatus comprising: first means coupled to receive said tri-state signal for limiting the variation of the tri-state signal in the floating regions to a single transition of one of said first and second signal threshold levels; and second means for sampling the tri-state signal as limited by the first means in relation to the preselected clock rate to identify its high and low state regions as high and low states, respectifely, and to identify its floating regions as being in the same state as the last previous one of the high and low state regions.
Claim 6
Independent Claim
217 words
An apparatus for generating a repeatable binary signal from a tri-state signal to characterize said tri-state signal for testing, both signals having the same preselected clock rate, and said tri-state signal being the output signal of a logic circuit wherein the output signal has a high state region defined as that region wherein the output stage of the logic circuit is clamped to a voltage level above a first signal threshold level, a low state region defined as that region when the output stage of the logic circuit is clamped to a voltage level below a second signal threshold level, and a floating region in those intervals when the output stage of the logic circuit is unclamped to any voltage level, said apparatus comprising: first means coupled to receive said tri-state signal for limiting the variation of the tri-state signal in the floating regions to a single transition of one of said first and second signal threshold levels; and second means for sampling the tri-state signal as limited by the first means in relation to the preselected clock rate to identify its high and low state regions as high and low states, respectifely, and to identify its floating regions as being in the same state as the last previous one of the high and low state regions.
Claim 7
Dependent Claim
72 words
An apparatus for generating a repeatable binary signal as in claim 4 wherein said first means includes: input means coupled to receive said tri-state signal; and a resistor with one end connected to the input means and the second end coupled to receive a preselected voltage level to pull the signal level in the floating regions of the tri-state signal toward a signal level intermediate said first and second signal threshold levels.
Claim 8
Dependent Claim
63 words
An apparatus for generating a repeatable binary signal as in claim 4 wherein said second means includes: transmission gate means coupled to said first means for sampling the tri-state signal as limited by the first means at the preselected clock rate; and hysteresis amplifier means coupled to the transmission gate means for identifying the states of the various regions of the sampled signal.
Claim 9
Dependent Claim
195 words
An apparatus for generating a repeatable binary signal as in claim 4 wherein said second means includes: first comparator means coupled to receive the tri-state signal as limited by, and from, said first means for generating a first binary signal having a high state when the limited tri-state signal level exceeds said first signal threshold level and a low state otherwise; second comparator means coupled to receive the tri-state signal as limited by, and from, said first means for generating a second binary signal having a high state when the limited tri-state signal level exceeds said second signal threshold level and a low state otherwise; and state machine means coupled to receive said first and second binary signals for generating in relation to the preselected clock rate, the repeatable binary signal having a high state region when both first and second binary signals are in the high state, a low state region when both first and second binary signals are in the low state, and the last previous one of the high and low states when the first binary signal is in the low state and the second binary signal is in the high state.
Claim 10
Dependent Claim
76 words
An apparatus for generating a repeatable binary signal as in claim 7 wherein said state machine means includes: inverter means for inverting the states of said second binary signal; and a J-K flip-flop coupled to receive said first binary signal at its J terminal, and the inverted second binary signal at its K terminal to generate at its Q terminal in response to the preselected clock rate signal on its clock terminal the repeatable binary signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-23 | 1984-03-24 | 1984-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-23 | 1988-03-24 | 1988-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-23 | 1992-03-24 | 1992-09-23 | $7700.00 | Window Closed / Lapsed |