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US4223237A Expired / Lapsed US ⏱️ 0.0 years remaining

Trigger pulse forming circuit

Assignee: Trio KK
•
Filing: 1978-12-08
•
Granted: 1980-09-16
•
Expires: 1998-12-08
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Abstract

Abstract A trigger pulse forming circuit comprising a first power supply; a second power supply whose voltage is less than that of the first power supply, a differential amplifier including a first transistor whose operating voltage is supplied from the first power supply and a second transistor whose operating voltage is supplied from a second power supply, at least the first transistor being adapted for application thereto of an input pulse signal; a load resistor connected to an output terminal of the first transistor; an integrating circuit connected to an output terminal of the second transistor; and a third transistor whose base and collector are connected respectively to opposite ends of the integrating circuit and its emitter is connected to the output terminal of the first transistor whereby the trigger pulse output is obtained from the output terminal of the first transistor. A diode may preferably also be included, the anode of the diode being connected to the output terminal of the second transistor and the cathode thereof being connected to the second power supply whereby the probability of the trigger pulse output saturating the transistors of the next stage is substantially lessened.

Inventors

  • 👤 Tsuneo Yamada
  • 👤 Yukihiko Miyamoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 22:04
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 161 words
A trigger pulse forming circuit comprising a first power supply; a second power supply having a common polarity with said first power supply whose voltage level is different than that of said first power supply; a differential amplifier including a first transistor whose operating voltage is supplied from the first power supply and a second transistor whose operating voltage is supplied from a second power supply, at least said first transistor being adapted for application thereto of an input pulse signal; a load resistor connected between an output terminal of said first transistor and said second power supply; an integrating circuit connected between an output terminal of said second transistor and said first power supply; and a third transistor whose base and collector are connected respectively to opposite ends of said integrating circuit and its emitter is connected to the output terminal of said first transistor whereby the trigger pulse output is obtained from the output terminal of said first transistor.
Claim 2
Dependent Claim 161 words
A trigger pulse forming circuit comprising a first power supply; a second power supply having a common polarity with said first power supply whose voltage level is different than that of said first power supply; a differential amplifier including a first transistor whose operating voltage is supplied from the first power supply and a second transistor whose operating voltage is supplied from a second power supply, at least said first transistor being adapted for application thereto of an input pulse signal; a load resistor connected between an output terminal of said first transistor and said second power supply; an integrating circuit connected between an output terminal of said second transistor and said first power supply; and a third transistor whose base and collector are connected respectively to opposite ends of said integrating circuit and its emitter is connected to the output terminal of said first transistor whereby the trigger pulse output is obtained from the output terminal of said first transistor.
Claim 3
Dependent Claim 34 words
A trigger pulse forming circuit as in claim 1 including a diode whose anode is connected to the output terminal of said second transistor and whose cathode is connected to said first power supply.
Claim 4
Dependent Claim 46 words
Circuitry as in claim 2 including output circuitry connected to said output terminal of said first transistor, said output circuitry including transistors whereby the probability of said trigger pulse output saturating the output circuitry transistors is substantially lessened due to the clamping action of said diode.
Claim 5
Dependent Claim 19 words
Circuitry as in claim 3 where said trigger pulse forming circuit and output circuitry are each emitter-coupled differential amplifiers.
Claim 6
Dependent Claim 24 words
A trigger pulse forming circuit as in claim 1 where said second power supply voltage is greater than that of said first power supply.
Claim 7
Dependent Claim 15 words
Circuitry as in claim 1 where said trigger pulse forming circuit is an integrated circuit.

References Cited (Backward Citations)

US3213290A Cited
US3454792A Cited
US3702944A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-09-16 1984-03-17 1984-09-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-09-16 1988-03-17 1988-09-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-09-16 1992-03-17 1992-09-16 $7700.00 Window Closed / Lapsed

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