US4220979A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bias level setting circuit for tape recorders with staircase high frequency signal
Assignee: Victor Company of Japan Ltd
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Filing: 1979-03-28
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Granted: 1980-09-02
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Expires: 1999-03-28
Abstract
Abstract An automatic bias level setting circuit for tape recorders includes a variable loss attenuator for stepwisely increasing the level of a high frequency bias signal which is superposed on a constant amplitude audio test signal. The recorded signal is detected by means of an envelope detector coupled to the playback head and fed into a resettable integrator for integrating the input signal in response to each stepwise variation of the signal to generate a series of sawtooth waves. The output of the integrator is coupled to a maximum peak detector to detect the maximum peak point of the recorded test signal to determine an optimum bias level in relation to the detected peak point.
Inventors
- 👤 Masatsugu Kitamura
- 👤 Hideo Onoye
- 👤 Masami Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 03:21
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/02; G11B5/027; G11B5/03; G11B5/035
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
200 words
An automatic bias level setting circuit for a tape recorder having a bias oscillator for generating an ultransonic frequency signal of a constant amplitude, comprising: means for stepwisely varying the signal level of said ultrasonic frequency bias signal as a function of time for application to an electromagnetic transducer head of said tape recorder operating as a recording head; a source for generating an audible frequency test signal of a constant amplitude for application to said recording head to record said test signal in superposition with said stepwisely varying bias signal; an envelope detector connected to said electromagnetic transducer head of the tape recorder operating as a playback head to detect the envelope of said recorded signal; a resettable integrator connected to the output of said envelope detector for integrating a signal from said envelope detector; means for resetting said integrator in response to a stepwise variation of said signal from said envelope detector; means for detecting the maximum value of a signal from said integrator; and means connected to said maximum detecting means for determining a signal level corresponding to a predetermined ratio of said detected maximum value and holding said stepwisely varying means to said determined signal level.
Claim 2
Dependent Claim
200 words
An automatic bias level setting circuit for a tape recorder having a bias oscillator for generating an ultransonic frequency signal of a constant amplitude, comprising: means for stepwisely varying the signal level of said ultrasonic frequency bias signal as a function of time for application to an electromagnetic transducer head of said tape recorder operating as a recording head; a source for generating an audible frequency test signal of a constant amplitude for application to said recording head to record said test signal in superposition with said stepwisely varying bias signal; an envelope detector connected to said electromagnetic transducer head of the tape recorder operating as a playback head to detect the envelope of said recorded signal; a resettable integrator connected to the output of said envelope detector for integrating a signal from said envelope detector; means for resetting said integrator in response to a stepwise variation of said signal from said envelope detector; means for detecting the maximum value of a signal from said integrator; and means connected to said maximum detecting means for determining a signal level corresponding to a predetermined ratio of said detected maximum value and holding said stepwisely varying means to said determined signal level.
Claim 3
Dependent Claim
108 words
An automatic bias level setting circuit as claimed in claim 1, wherein said maximum detector comprises a comparator having an input terminal connected to the output of said resettable integrator and another input biased at a reference level to generate a signal at one of two discrete values depending on whether the output signal from said integrator is above or below said reference value and means for successively measuring the time period of said signal from said comparator in response to said resetting means and detecting when the measured time period of a previously generated signal is smaller than the measured time period of a subsequently generated signal.
Claim 4
Dependent Claim
65 words
An automatic bias level setting circuit as claimed in claim 1, wherein said resetting means comprises a pulse source and means for introducing a delay interval to a pulse from said pulse source corresponding to the time a magnetic tape travels from the position of said recording head to the position of the playback head for resetting said integrator in response to the delayed pulse.
Claim 5
Dependent Claim
75 words
An automatic bias level setting circuit as claimed in claim 3, wherein said stepwisely varying means comprises a variable loss attenuator for passing a signal from said bias oscillator to said recording head and a shift register receptive of pulses from said pulse source for generating a binary signal upon receipt of each said pulse for causing said variable loss attenuator to decrease the amount of its loss stepwisely in accordance with said binary signal.
Claim 6
Dependent Claim
44 words
An automatic bias level setting circuit as claimed in claim 1, wherein said resetting means comprises means connected to said envelope detector for detecting stepwise variations of a signal from said envelope detector and resetting said integrator in response to the detected stepwise variation.
Claim 7
Dependent Claim
56 words
An automatic bias level setting circuit as claimed in claim 5, further comprising means for operating said tape recorder in one of a plurality of selectable operational modes including means for permitting said stepwisely varying bias signal and said test signal to be recorded simultaneously on a tape and permitting the recorded signal to be reproduced.
Claim 8
Dependent Claim
84 words
An automatic bias level setting circuit as claimed in any one of the preceding claims, further comprising a first equalizer for equalizing a recording signal and a second equalizer for equalizing a signal from said playback head, each of said first and second equalizers having a plurality of selectable equalization characteristics, and means for detecting whether the output signal from said integrator is above or below a preselected reference level and selecting one of said equalization characteristics in response to the detected output signal.
References Cited (Backward Citations)
US4038692A
Cited
US4011585A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-02 | 1984-03-03 | 1984-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-02 | 1988-03-03 | 1988-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-02 | 1992-03-03 | 1992-09-02 | $7700.00 | Window Closed / Lapsed |