Superheterodyne receiver of scanning type with indicator means to display received frequency and frequency being stored in memory
Abstract
Abstract A superheterodyne receiver of a scanning type, comprising a high frequency amplifier, a mixer, a local oscillator, an interdmediate frequency amplifier, a detector, an audio frequency amplifier, a loud speaker, and an automatic scanning/manual scanning selecting switch, said local oscillator comprising a digital frequency synthesizer comprising a voltage controlled oscillator, a programmable frequency divider for dividing the frequency of the output from the voltage controlled oscillator, a reference oscillator, a random access memory for storing the information concerning the rate of the frequency division by the frequency divider, and a phase detector for phase detecting the frequencies of the outputs from the reference oscillator and the frequency divider for providing a control voltage to said voltage controlled oscillator, said receiver further comprising an astable multivibrator for generating pulses for scanning the frequencies of the receiving bands, a counter for counting the pulses from the astable multivibrator, a decoder for decoding the count output from the counter, a plurality of light emitting diodes correspondingly coupled to the decoder output, a plurality of switching transistors connected to a plurality of bit parallel outputs of the random access memory, a plurality of switches for presetting in the random access memory the information concerning the rate of frequency division by the frequency divider corresponding to a predetermined channel, a squelch circuit responsive to a noise detected output obtained when the said detector detects a noise for disabling the audio frequency amplifier, a plurality of undesired channel setteing switches for presetting a channel reception of which is not desired, and a switching transistor responsive to the reception of the frequency corresponding to the channel as set by the said undesired channel setting switch for providing a potential for forcibly enabling the said squelch circuit for disabling the audio frequency amplifier.
Inventors
- 👤 Eigo Imamura
Bibliographic Details
Claims Analysis
Total Claims: 3References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1983-08-19 | 1984-02-18 | 1984-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-08-19 | 1988-02-18 | 1988-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-08-19 | 1992-02-18 | 1992-08-19 | $7700.00 | Window Closed / Lapsed |