US4216546A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency bandwidth tuning system and method
Assignee: United States Department of the Army
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Filing: 1978-08-15
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Granted: 1980-08-05
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Expires: 1998-08-15
Abstract
Abstract An electronic system for scanning across a range of received signals and aining a digital representation of a predetermined position, for example, the mid-point, of the bandwidth of the received signal, without having to ascertain directly the frequency at said predetermined position. The system can include a homodyne receiver (zero-beat reception) using a voltage controlled local oscillator or a superheterodyne receiving using a local oscillator for producing an intermediate frequency.
Inventors
- 👤 Eric S. Litt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:32
CPC Classifications
H; H04; H04K; H04K3/00; H04K3/40; H04K3/45; H04K3/42
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
319 words
A clocked receiving system including a receiver having a controllable oscillator and capable of automatically sensing the frequency at a prespecified position within the bandwidth of a received input signal of frequency unknown at the receiving system, said receiver producing pulses at a difference frequency between said oscillator and said received signal, comprising clock means for providing a series of clock pulses at a given rate, clock rate division means responsive to said clock means for providing clock pulses at a reduced rate which is less than said given rate by an amount dependent upon said prespecified position, oscillator frequency control means including a first up-down counter responsive to pulses from said clock means for incrementally controlling the oscillator tuning frequency of said receiver over the bandwidth of said receiver as a function of the count of said first counter to effect an incremental scanning of the oscillator frequency back and forth over a range of discrete frequency increments during the operation of said clock means, measuring counter means including a second up-down counter responding to the presence of difference frequency pulses and to the output of said clock rate division means for counting up at said reduced rate during the presence of said pulses from an initial count up to a threshold count attained at occurrence of a difference frequency pulse corresponding to the maximum bandwidth of said received input signal, said measuring counter means including a control circuit responsive to cessation of said difference frequency pulses for changing the direction of counting of said first and second counters and for changing the counting rate of said second counter to that of said clock means, and clock inhibiting means responding to attainment of the initial count by the down-counting second counter for maintaining the incremental frequency count of said first counter and to hold the receiver at said predetermined position within the bandwidth of said received input signal.
Claim 2
Dependent Claim
319 words
A clocked receiving system including a receiver having a controllable oscillator and capable of automatically sensing the frequency at a prespecified position within the bandwidth of a received input signal of frequency unknown at the receiving system, said receiver producing pulses at a difference frequency between said oscillator and said received signal, comprising clock means for providing a series of clock pulses at a given rate, clock rate division means responsive to said clock means for providing clock pulses at a reduced rate which is less than said given rate by an amount dependent upon said prespecified position, oscillator frequency control means including a first up-down counter responsive to pulses from said clock means for incrementally controlling the oscillator tuning frequency of said receiver over the bandwidth of said receiver as a function of the count of said first counter to effect an incremental scanning of the oscillator frequency back and forth over a range of discrete frequency increments during the operation of said clock means, measuring counter means including a second up-down counter responding to the presence of difference frequency pulses and to the output of said clock rate division means for counting up at said reduced rate during the presence of said pulses from an initial count up to a threshold count attained at occurrence of a difference frequency pulse corresponding to the maximum bandwidth of said received input signal, said measuring counter means including a control circuit responsive to cessation of said difference frequency pulses for changing the direction of counting of said first and second counters and for changing the counting rate of said second counter to that of said clock means, and clock inhibiting means responding to attainment of the initial count by the down-counting second counter for maintaining the incremental frequency count of said first counter and to hold the receiver at said predetermined position within the bandwidth of said received input signal.
Claim 3
Dependent Claim
36 words
A clocked receiving system according to claim 1 wherein said prespecified position is at the center of the bandwidth of the received input signal and said reduced clock rate is half that of said clock means.
Claim 4
Dependent Claim
34 words
A clocked receiving system according to claim 1 wherein said frequency control means includes a digital-to-analog converter for converting the digital count of said first counter to a tuning voltage for said controllable oscillator.
Claim 5
Dependent Claim
35 words
A clocked receiving system according to claim 1 wherein said frequency control means includes a digital-to-synchronous converter for converting the digital count of said first counter to a mechanical tuning control of said controllable oscillator.
Claim 6
Dependent Claim
54 words
A clocked receiving system according to claim 1 further including an integrating detector responsive to said difference frequency pulses for deriving an integrated pulse during the continued presence of said difference frequency pulses, and wherein said measuring counter means is receptive of said integrated pulse and said clock pulse for controlling said second counter.
Claim 7
Dependent Claim
18 words
A clocked receiving system according to claim 5 wherein said integrating detector is controlled by said clock means.
Claim 8
Dependent Claim
54 words
A clocked receiving system according to claim 5 wherein said oscillator frequency control means further includes a control assembly for said first counter and the measuring counter control circuit includes a bistable circuit an output of which increases upon cessation of said integrated pulse for introducing a count direction-changing input to said first counter.
Claim 9
Dependent Claim
21 words
A clocked receiving system according to claim 1 wherein said clock inhibiting means is the borrow output from said measuring counter.
Claim 10
Dependent Claim
31 words
A clocked receiving system according to claim 5 further including a validity testing circuit and wherein said measuring counter means is also receptive to the output of said validity testing circuit.
References Cited (Backward Citations)
US3571760A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-08-05 | 1984-02-04 | 1984-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-08-05 | 1988-02-04 | 1988-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-08-05 | 1992-02-04 | 1992-08-05 | $7700.00 | Window Closed / Lapsed |