US4216540A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable polynomial generator
Assignee: Bank of America NA
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Filing: 1978-11-09
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Granted: 1980-08-05
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Expires: 1998-11-09
Abstract
Abstract A polynomial generator for use in an error code correction system consists of an input data multiplexer for determining the mode of operation, a plurality of polynomial enable gates to allow insertion of a predetermined polynomial, a plurality of check character generating gates divided into a first group and a second group for forming an output polynomial from the input data and the predetermined polynomial, an output holding register and a pair of decode gates for constantly monitoring the contents of the holding register to provide an indication of either of two particular conditions.
Inventors
- 👤 Jeff R. McSpadden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:34
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/65; H03M13/6508; H03M13/6516; H03M13/03; H03M13/05; H03M13/13; H03M13/15
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
211 words
A programmable polynomial generator for use in error correction systems comprising: means for receiving a plurality of polynomial enable input signals representing an input polynomial, means for receiving input data signals representing bits of an input operand, a data input multiplexer connected to said means for receiving input data signals for selectively multiplexing said signals in a particular pattern from a predetermined number of patterns, a plurality of polynomial enable gates adapted to respond to at least one control signal, said each of gates being connected to said means for receiving a plurality of polynomial enable input signals a plurality of check character generating gates, each of said gates being connected to receive signals from said data input multiplexer and from an associated one of said polynomial enable gates, a holding register adapted to respond to at least one control signal connected for receiving signals from each of said plurality of check character generating gates, a first decode gate connected to the output signals of said holding register to provide a decode signal if the contents of said register is all zero, and a second decode gate connected to receive output signals from said holding register to provide a decode signal if the contents of said register are a predetermined quantity.
Claim 2
Dependent Claim
211 words
A programmable polynomial generator for use in error correction systems comprising: means for receiving a plurality of polynomial enable input signals representing an input polynomial, means for receiving input data signals representing bits of an input operand, a data input multiplexer connected to said means for receiving input data signals for selectively multiplexing said signals in a particular pattern from a predetermined number of patterns, a plurality of polynomial enable gates adapted to respond to at least one control signal, said each of gates being connected to said means for receiving a plurality of polynomial enable input signals a plurality of check character generating gates, each of said gates being connected to receive signals from said data input multiplexer and from an associated one of said polynomial enable gates, a holding register adapted to respond to at least one control signal connected for receiving signals from each of said plurality of check character generating gates, a first decode gate connected to the output signals of said holding register to provide a decode signal if the contents of said register is all zero, and a second decode gate connected to receive output signals from said holding register to provide a decode signal if the contents of said register are a predetermined quantity.
Claim 3
Dependent Claim
72 words
The device of claim 1 wherein said plurality of check character generating gates are formed in a first group and a second group, said first group of said check character generating gates receiving an input from said data input multiplexer, and said second group of said check character generating gates receiving first input from said polynomial enable gates and a second input from said first group of said check character generating gates.
Claim 4
Dependent Claim
31 words
The device of claim 2 wherein said first group of check character generating gates receives a first input from said data input multiplexer and a second input from said holding register.
Claim 5
Dependent Claim
29 words
The device of claim 3 where the second input to said first group of check character generating gates is the same as the input to the second decode gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-08-05 | 1984-02-04 | 1984-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-08-05 | 1988-02-04 | 1988-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-08-05 | 1992-02-04 | 1992-08-05 | $7700.00 | Window Closed / Lapsed |