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US4216531A Expired / Lapsed US ⏱️ 0.0 years remaining

Finite field multiplier

Assignee: Bank of America NA
•
Filing: 1978-11-17
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Granted: 1980-08-05
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Expires: 1998-11-17
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Abstract

Abstract A multiplier for use with polynomials in an error correction system wherein the multiplier and multiplicand are first encoded from m bits to N bits, where N is greater than m, and wherein the multiplication is accomplished on a bit basis by arrays of AND gates and where the resultant product is decoded from R bits to S bits where S is less than R.

Inventors

  • 👤 Sou-Hsiung J. Chiu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 10:08
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/15; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F7/00; G06F7/60; G06F7/72; G06F7/724

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 343 words
A finite field multiplier for forming the product of two operands A and B expressed as a plurality of binary bits, where each operand is of the same length and wherein the relationship 2 m -1 is divisible to form an integer by m+1 wherein m is the number of bits in said operands, wherein said multiplier comprises, means for receiving an A operand of the form A=a 0 +a 1 x+a 2 x 2 +a 3 x 3 +. . . +a m-1 x m-1 means for receiving a B operand of the form B=b 0 +b 1 x+b 2 x 2 +b 3 x 3 +. . . +b m-1 x m-1 a first transpose network means for transforming the A operand into the equivalent form A'=a' 0 +a' 1 r+a' 2 r 2 +a' 3 r 3 +a' 4 r 4 +. . . +a' m r m where r m+1 =x 2m-1 =1 wherein said first transpose network means is comprised of Exclusive OR gates, a second transpose network means for transforming the B operand into the equivalent form B'=b' 0 +b' 1 r+b' 2 r 2 +b' 3 r 3 +b' 4 r 4 +. . . +b' m r m where r m+1 =x 2m-1 =1 wherein said second transpose network means is comprised of Exclusive OR gates, a plurality of first multiplier busses connected to receive the output of said first transpose network means, a plurality of second multiplier busses connected to receive the output of said second transpose network means, a plurality of AND gate groups connected in array form to said first and second plurality of multiplier busses, a plurality of product busses, at least one Exclusive OR gate connected to each of said AND gate groups and having an output connected to one of said product busses, an output inverse transpose network connected to said product busses for producing a product ##EQU15## wherein said inverse transpose network is comprised of Exclusive OR gates and the resultant product is a sequence of m bits.
Claim 2
Dependent Claim 343 words
A finite field multiplier for forming the product of two operands A and B expressed as a plurality of binary bits, where each operand is of the same length and wherein the relationship 2 m -1 is divisible to form an integer by m+1 wherein m is the number of bits in said operands, wherein said multiplier comprises, means for receiving an A operand of the form A=a 0 +a 1 x+a 2 x 2 +a 3 x 3 +. . . +a m-1 x m-1 means for receiving a B operand of the form B=b 0 +b 1 x+b 2 x 2 +b 3 x 3 +. . . +b m-1 x m-1 a first transpose network means for transforming the A operand into the equivalent form A'=a' 0 +a' 1 r+a' 2 r 2 +a' 3 r 3 +a' 4 r 4 +. . . +a' m r m where r m+1 =x 2m-1 =1 wherein said first transpose network means is comprised of Exclusive OR gates, a second transpose network means for transforming the B operand into the equivalent form B'=b' 0 +b' 1 r+b' 2 r 2 +b' 3 r 3 +b' 4 r 4 +. . . +b' m r m where r m+1 =x 2m-1 =1 wherein said second transpose network means is comprised of Exclusive OR gates, a plurality of first multiplier busses connected to receive the output of said first transpose network means, a plurality of second multiplier busses connected to receive the output of said second transpose network means, a plurality of AND gate groups connected in array form to said first and second plurality of multiplier busses, a plurality of product busses, at least one Exclusive OR gate connected to each of said AND gate groups and having an output connected to one of said product busses, an output inverse transpose network connected to said product busses for producing a product ##EQU15## wherein said inverse transpose network is comprised of Exclusive OR gates and the resultant product is a sequence of m bits.

References Cited (Backward Citations)

US4037093A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-08-05 1984-02-04 1984-08-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-08-05 1988-02-04 1988-08-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-08-05 1992-02-04 1992-08-05 $7700.00 Window Closed / Lapsed

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