US4216379A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low voltage bias circuit for a photo-diode
Assignee: Allegro Microsystems LLC
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Filing: 1978-10-26
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Granted: 1980-08-05
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Expires: 1998-10-26
Abstract
Abstract A low-voltage bias circuit for a photo-diode includes first and second bipolar transistors with a common base connection and grounded emitters, the photo-diode being connected between the emitter of the first transistor and ground in the reverse polarity direction. A current-mirror circuit uses as the reference current the collector current from the first transistor, which is essentially the photo-current, and produces a feed-back current through the base-emitter junction of the second transistor to hold the voltage across the photo-diode at a near zero value for a wide range in values of photo-current. Thus there is minimum delay in the response of the photo-current to step-functions of the incident light.
Inventors
- 👤 Robert C. Genesi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:02
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/78; H03K17/795; H10; H10F; H10F77/00; H10F77/95; H10F77/953
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
166 words
A low voltage bias circuit for a photo-diode comprising two d.c. power supply busses; a first bipolar transistor; a bipolar input device having at least one p-n junction, said photo-diode being connected between the emitter of said first transistor and one of said busses, said p-n junction being connected between the base of said first transistor and said one buss, the polarity of connection of the base-emitter junction of said first transistor being opposite to that of said p-n junction and of said photo-diode in the circuit loop containing all three in series whereby the photo-current generated by said photo-diode in response to light impinging thereon flows in the collector of said first transistor when said first transistor is on; and a current mirror circuit means being connected to the other of said busses and having an input connected to said collector of said first transistor for producing a feed-back current in the forward direction through said p-n junction that is substantially proportional to said photo-current.
Claim 2
Dependent Claim
166 words
A low voltage bias circuit for a photo-diode comprising two d.c. power supply busses; a first bipolar transistor; a bipolar input device having at least one p-n junction, said photo-diode being connected between the emitter of said first transistor and one of said busses, said p-n junction being connected between the base of said first transistor and said one buss, the polarity of connection of the base-emitter junction of said first transistor being opposite to that of said p-n junction and of said photo-diode in the circuit loop containing all three in series whereby the photo-current generated by said photo-diode in response to light impinging thereon flows in the collector of said first transistor when said first transistor is on; and a current mirror circuit means being connected to the other of said busses and having an input connected to said collector of said first transistor for producing a feed-back current in the forward direction through said p-n junction that is substantially proportional to said photo-current.
Claim 3
Dependent Claim
73 words
The bias circuit of claim 1 wherein said current-mirror means is comprised of a second and a third bipolar transistor of polarity type opposite to that of said first transistor, said second and third transistors having their bases connected to each other and their emitters connected to said other buss, one collector of said second transistor being said current-mirror input and one collector of said second transistor being connected to said p-n junction.
Claim 4
Dependent Claim
45 words
The bias circuit of claim 1 additionally comprising a current amplifying means that is connected to the collector of said first transistor for amplifying the current flowing in said first transistor collector and providing an amplified output current which is substantially proportional to said photo-current.
Claim 5
Dependent Claim
21 words
The bias circuit of claim 3 additionally comprising an integrating capacitor being connected to the output of said current amplifying means.
Claim 6
Dependent Claim
35 words
The bias circuit of claim 1 additionally comprising a control current generator means that is connected to the collector of said first transistor for generating a control current which is substantially proportional to said photo-current.
Claim 7
Dependent Claim
86 words
The bias circuit of claims 3, 4 or 5 additionally comprising a differential amplifying means for amplifying the voltage across said integrating capacitor, said differential amplifying means having a pair of amplifying transistors whose emitters have a common connection; and a variable current source means the output of which is connected to said emitters of said amplifying transistors and the input of which is connected to said generating means for producing at said commonly connected emitters an emitter current which is substantially proportional to said photo-current.
Claim 8
Dependent Claim
26 words
The bias circuit of claim 1 wherein the junction area of said p-n junction is substantially equal to the base-emitter junction area of said first transistor.
Claim 9
Dependent Claim
35 words
The bias circuit of claim 1 wherein said bipolar input device is an input bipolar transistor, said p-n junction thereof being the base-emitter junction, the collector and base of said input transistor being connected together.
Claim 10
Dependent Claim
27 words
The bias circuit of claim 1 additionally comprising a bias-starting means for turning on said first transistor after applying a d.c. supply voltage between said two busses.
Claim 11
Dependent Claim
40 words
The bias circuit of claim 1 wherein the product of said feed-back current and the area of said p-n junction is about 5 times the product of said photo-current and the area of said base-emitter junction of said first transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-08-05 | 1984-02-04 | 1984-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-08-05 | 1988-02-04 | 1988-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-08-05 | 1992-02-04 | 1992-08-05 | $7700.00 | Window Closed / Lapsed |