Semiconductor device and method

Claim 2

A semiconductor device formed at a face of a semiconductor body having particular regions in the body at said face and layers on the body at said face, the regions and layers determining the operative characteristics of the device, at least one of said layers being offset with respect to an underlying one of the regions sufficiently to produce a portion of misregistration thereby correspondingly creating a potentially defective area, and an ion implanted region at said face within the semiconductor body at said potentially defective area, said ion implanted region having a charge carrier concentration greater than semiconductor material underlying it to prevent inversion from ambient impurities and thereby prevent potential defects from developing.

Claim 3

A semiconductor device formed at a face of a semiconductor body having regions and overlying layers at said face determining the operative characteristics of the device one of said layers over one of said regions being offset with respect to such region sufficiently to expose a surface portion having a thin coating thereon and vulnerable to surface inversion, and an ion implanted region within the face of the body essentially conforming to said exposed surface portion and having a charge carrier concentration greater than that of adjacent material of the semiconductor body to prevent surface inversion.

Claim 4

A semiconductor device formed at a face of a semiconductor body having regions and overlying layers at said face determining the operative characteristics of the device one of said layers over one of said regions being offset with respect to such region sufficiently to expose a surface portion having a thin coating thereon and vulnerable to surface inversion, and an ion implanted region within the face of the body essentially conforming to said exposed surface portion and having a charge carrier concentration greater than that of adjacent material of the semiconductor body to prevent surface inversion.

Claim 5

A semiconductor integrated circuit including an insulated gate field effect transistor and having a large region of one conductivity type and at least two spaced apart regions adjacent one major surface of said large region having a different conductivity type to provide source and drain regions, a thin insulating layer overlying a defined area between said source and drain regions and contiguous to said defined area, a gate including a conducting member overlying at least some of said thin insulating layer and overlying a part only of said defined area whereby a portion of said defined area is covered only by said thin insulating layer, said portion being within said defined area and corresponding to the part of said defined area not having said conducting member overlying it, said portion containing charge carrier concentration greater than that part having said conducting member overlying it.

Claim 6

A semiconductor integrated circuit including an insulated gate field effect transistor and having a large region of one conductivity type and at least two spaced apart regions adjacent one major surface of said large region having a different conductivity type to provide source and drain regions, a thin insulating layer overlying a defined area between said source and drain regions and contiguous to said defined area, a gate including a conducting member overlying at least some of said thin insulating layer and overlying a part only of said defined area whereby a portion of said defined area is covered only by said thin insulating layer, said portion being within said defined area and corresponding to the part of said defined area not having said conducting member overlying it, said portion containing charge carrier concentration greater than that part having said conducting member overlying it.

Claim 7

A semiconductor device formed at a face of a semiconductor body having particular regions and layers at said face determining the operative characteristics of the device one of said layers being physically positioned with respect to one of the regions to produce areas of overlapping one by the other, but wherein said overlapping is not complete thereby exposing at least a portion of one of said regions, said portion of one of said regions having a charge carrier concentration at said face greater than that of semiconductor material underlying it to prevent inversion of said portion from ambient impurities and thereby prevent potential defects from developing.

Claim 8

A semiconductor device formed at a face of a semiconductor body having particular regions and layers at said face determining the operative characteristics of the device one of said layers being physically positioned with respect to one of the regions to produce areas of overlapping one by the other, but wherein said overlapping is not complete thereby exposing at least a portion of one of said regions, said portion of one of said regions having a charge carrier concentration at said face greater than that of semiconductor material underlying it to prevent inversion of said portion from ambient impurities and thereby prevent potential defects from developing.

Claim 9

A read-only-memory of the type comprising a plurality of insulated gate field effect transistors at a face of a semiconductor body, each field effect transistor having spaced apart source and drain regions formed by heavily doped semiconductor material of conductivity type opposite that of underlying material in the body and having a gate positioned above a channel area between the source and drain regions, the gate being conductive and being insulated from the channel area by an insulating coating on the face, wherein the improvement comprises an ion implanted region in the channel area formed after the gate is in place, the ion implanted region being adjacent to and aligned with the gate and extending to the source and the drain of at least some of the transistors, the concentration of impurities in the ion implanted region exceeding that in the channel area by a significant amount.

Claim 10

A read-only-memory of the type comprising a plurality of insulated gate field effect transistors at a face of a semiconductor body, each field effect transistor having spaced apart source and drain regions formed by heavily doped semiconductor material of conductivity type opposite that of underlying material in the body and having a gate positioned above a channel area between the source and drain regions, the gate being conductive and being insulated from the channel area by an insulating coating on the face, wherein the improvement comprises an ion implanted region in the channel area formed after the gate is in place, the ion implanted region being adjacent to and aligned with the gate and extending to the source and the drain of at least some of the transistors, the concentration of impurities in the ion implanted region exceeding that in the channel area by a significant amount.

Claim 11

A read-only-memory according to claim 5 wherein the gate is metal and the ion implanted region has an increased concentration of impurity of conductivity type opposite that of the source and drain regions.

Claim 12

A read-only-memory according to claim 6 wherein the ion implanted region extends along the channel area from source to drain regions.

Claim 13

A read-only-memory according to claim 5 wherein the threshold of the ion implanted regions is increased relative to that of the ion implanted channel areas.