US4210879A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Four-phase staggered shift keying modulator system
Assignee: Individual
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Filing: 1978-06-05
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Granted: 1980-07-01
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Expires: 1998-06-05
Abstract
Abstract A four phase staggered phase shift keying modulator system having means to modulate a voltage controlled oscillator generating the carrier by positive or negative pulses of a predetermined duration to shift the phase of the carrier by +90 DEG or -90 DEG , the positive or negative being produced by individual coding of a series of applied pulses.
Inventors
- 👤 Jean-Pierre R. Poitevin
- 👤 Pierre C. Brossard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:21
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/20; H04L27/2032; H04L27/2053; H04L27/206; H04L27/2067; H04L27/2078
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
186 words
A four phase staggered shift keying modulator employing transition coding by a series of binary digits in which each bit does or does not modify the phase condition of a carrier according to transition coding by a phase shift representing its contribution depending on its value defined by the two bits which precede it, including a voltage controlled oscillator means for generating the carrier, a control circuit, means to apply the series of bits to the input of the control circuit, the control circuit generating positive or negative pulses of a duration less than or equal to the duration of one bit of the series, means to apply the positive or negative pulses from the control circuit to the input of the voltage controlled oscillator, each pulse shifting the phase of the output frequency of the oscillator by +90° or -90° depending on its sign, wherein the 0 bits do not generate any pulses and the 1 bits generate a positive or a negative pulse, the sign of two successive pulses being modified or not depending on the parity of the number of intermediate 0 bits.
Claim 2
Dependent Claim
186 words
A four phase staggered shift keying modulator employing transition coding by a series of binary digits in which each bit does or does not modify the phase condition of a carrier according to transition coding by a phase shift representing its contribution depending on its value defined by the two bits which precede it, including a voltage controlled oscillator means for generating the carrier, a control circuit, means to apply the series of bits to the input of the control circuit, the control circuit generating positive or negative pulses of a duration less than or equal to the duration of one bit of the series, means to apply the positive or negative pulses from the control circuit to the input of the voltage controlled oscillator, each pulse shifting the phase of the output frequency of the oscillator by +90° or -90° depending on its sign, wherein the 0 bits do not generate any pulses and the 1 bits generate a positive or a negative pulse, the sign of two successive pulses being modified or not depending on the parity of the number of intermediate 0 bits.
Claim 3
Dependent Claim
144 words
A modulator as claimed in claim 1 including a logic inverter, means to connect the said series of bits to the input of the logic inverter, a flip-flop, the output of the logic inverter being connected to the complementary signal input of the flip-flop, a pair of AND gates, each gate having three inputs, each output of the flip-flop being connected to an input of a respective AND gate, means to connect said series of bits to a second input of each AND gate, means to connect a clock signal at the bit rhythm to a third input of each AND gate, and a transformer, the outputs of the AND gates being connected to the centre tapped primary winding of the transformer, the secondary winding of the transformer having one terminal earthed and the other terminal connected to the control input of the oscillator.
Claim 4
Dependent Claim
34 words
A modulator as claimed in claim 2 wherein the flip-flop is a delay flip-flop circuit having an output which is a delayed response to a pulse which occurs earlier in a binary pulse stream.
Claim 5
Dependent Claim
30 words
A modulator as claimed in claim 2 or claim 3 including an pulse shaping circuit connected between the output of the secondary winding and the control input of the oscillator.
Claim 6
Dependent Claim
130 words
A four-phase staggered shift keying modulator comprising means for receiving an input signal comprising a series of intermixed 1 and 0 bit signals and a series of clock signals, an output voltage controlled oscillator means, control circuit means responsive to said input and clock signals, means in said control circuit means for determining the parity of the number of 0 bits in said series of bit signals which immediately precede a 1 bit, means in said control circuit responsive to an even parity for delivering a positive pulse V(t) and responsive to an odd parity for delivering a negative pulse V(t), wherein V(t) is equal to ##EQU2## where: S is the modulation sensitivity of said oscillator means expressed by a frequency/voltage ratio, and T is the duration of one bit.
Claim 7
Dependent Claim
130 words
A four-phase staggered shift keying modulator comprising means for receiving an input signal comprising a series of intermixed 1 and 0 bit signals and a series of clock signals, an output voltage controlled oscillator means, control circuit means responsive to said input and clock signals, means in said control circuit means for determining the parity of the number of 0 bits in said series of bit signals which immediately precede a 1 bit, means in said control circuit responsive to an even parity for delivering a positive pulse V(t) and responsive to an odd parity for delivering a negative pulse V(t), wherein V(t) is equal to ##EQU2## where: S is the modulation sensitivity of said oscillator means expressed by a frequency/voltage ratio, and T is the duration of one bit.
Claim 8
Dependent Claim
41 words
The modulator of claim 5 wherein the phase of a signal emitted by the voltage-controlled oscillator means varies by 90°, and means responsive to said positive or negative pulse to select the direction of the phase change of said emitted signal.
References Cited (Backward Citations)
US3393380A
Cited
US4125817A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-07-01 | 1983-12-31 | 1984-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-07-01 | 1987-12-31 | 1988-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-07-01 | 1991-12-31 | 1992-07-01 | $7700.00 | Window Closed / Lapsed |