Optimum diversity combining circuit for a plurality of channels

Claim 2

An AM/AGC weighted diversity combiner circuit responsive to AGC and AM voltages from AGC loops (which include AGC integrators) of a plurality of receivers as well as respective instantaneous input signal and noise voltages of the receivers for combining a plurality of diversity signals whereby the output signal to noise ratio is maximized comprising: a. a plurality of log and summing circuits responsive to said AGC and AM voltages from said receivers for generating a plurality of independent weighting signals, each weighting signal being associated with a respective receiver; b. a plurality of weighting circuits; each respective weighting circuit responsive to respective said independent weighting signals and to respective said instantaneous input signal and noise voltages from respective said receivers for generating a plurality of respective independent weighted diversity signals, each weighted diversity signal being associated with a respective receiver; and c. means for summing said plurality of weighted diversity signals with said summed diversity signals being the output signal and noise voltages with maxmized signal-to-noise ratio.

Claim 3

The apparatus of claim 1 further including a high pass filter coupled to receive said output signal and noise voltages.

Claim 4

The apparatus of claim 1 wherein each said log and summing circuit includes means for generating a weighting signal e wi given by the following relationship e.sub.wi =e.sub.gi -log (e.sub.ai /V) where e ai =i th receiver AM voltage V=bias voltage of the AGC loop integrators.

Claim 5

The apparatus of claim 3 wherein said weighting signal generating means includes a. a direct-current logarithmic amplifer coupled to receive said AM voltage for generating a log signal; and b. an operational amplifier having a feedback resistor responsive to said log signal and said AGC voltage for generating said weighting signal.

Claim 6

An AM/AGC weighted diversity combiner circuit responsive to the AGC and AM voltages from AGC loops of a plurality of receivers as well as respective instantaneous input signal and noise voltages of the receivers for combining a plurality of diversity signals whereby the output signal to noise ratio is maximized comprising: a. a plurality of log and summing circuits responsive to said AGC and AM voltages from said receivers for generating a plurality of weighting signals, each weighting signal being associated with a respective receiver; b. a plurality of weighting circuits responsive to said weighting signals and to said instantaneous input signal and noise voltages from said receivers for generating a plurality of weighted diversity signals, each weighted diversity signal being associated with a respective receiver; c. each said weighting circuit including: a differential amplifier circuit having common emitters, said differential amplifier circuit being coupled to receive said weighting signal; a common emitter circuit responsive to said input signal and noise voltages and coupled to said common emitters of said differential amplifier circuit; and means responsive to said weighting signal and coupled to said differential amplifier circuit for selecting one of said weighting circuits as a reference channel; and d. means for summing said plurality of weighted diversity signals with said summed diversity signals being the output signal and noise voltages with maximized signal-to-noise ratio.

Claim 7

An AM/AGC weighted diversity combiner circuit responsive to the AGC and AM voltages from AGC loops of a plurality of receivers as well as respective instantaneous input signal and noise voltages of the receivers for combining a plurality of diversity signals whereby the output signal to noise ratio is maximized comprising: a. a plurality of log and summing circuits responsive to said AGC and AM voltages from said receivers for generating a plurality of weighting signals, each weighting signal being associated with a respective receiver; b. a plurality of weighting circuits responsive to said weighting signals and to said instantaneous input signal and noise voltages from said receivers for generating a plurality of weighted diversity signals, each weighted diversity signal being associated with a respective receiver; c. each said weighting circuit including: a differential amplifier circuit having common emitters, said differential amplifier circuit being coupled to receive said weighting signal; a common emitter circuit responsive to said input signal and noise voltages and coupled to said common emitters of said differential amplifier circuit; and means responsive to said weighting signal and coupled to said differential amplifier circuit for selecting one of said weighting circuits as a reference channel; and d. means for summing said plurality of weighted diversity signals with said summed diversity signals being the output signal and noise voltages with maximized signal-to-noise ratio.

Claim 8

The apparatus of claim 5 wherein said differential amplifier circuit comprises: a. a first transistor having a base, an emitter, and a collector; b. a second transistor having a base, an emitter, and a collector, said first and second transistor being substantially identical, said second transistor base being coupled to said selecting means, said second transistor emitter being coupled to said first transistor emitter, said first transistor collector being coupled to a second bias voltage, said weighted signal appearing on the collector of said second transistor; and c. a first resistor coupled between the base of said first transistor and said weighting signal; d. a second resistor coupled between the base of said first transistor and a reference voltage; e. a third resistor coupled between the collector of said first transistor and said first resistor; and f. a diode circuit for coupling said weighting signal to said first resistor.

Claim 9

The apparatus of claim 6 wherein said diode circuit includes a Schottky Barrier diode.

Claim 10

The apparatus of claim 6 wherein said common emitter circuit includes: a. a third transistor having an emitter, a collector, and a base, said third transistor collector being coupled to said first and second transistor emitters, said third transistor base being coupled to receive said input signal and noise voltages; b. a capacitor having a first and a second side, said first side being coupled to a reference voltage; and c. a fourth resistor being coupled between said third transistor emitter and said second side of said capacitor.

Claim 11

The apparatus of claim 8 wherein the values of said first (R 1 ) and second (R 2 ) resistors are given by the following relationships R.sub.1 /R.sub.2 =(K.sub.1 -2K.sub.3 /2K.sub.3) where K 3 =kT/q log e and k=Boltzman's constant T=Absolute Temperature q=electron charge e=2.71828 . . . log=logarithm to the base 10 K 1 =a constant unique to a particular receiver.

Claim 12

The apparatus of claim 5 wherein said selecting means includes a diode circuit responsive to said weighting signal.

Claim 13

The apparatus of claim 10 wherein said diode circuit includes: a. a diode; b. a first resistor in series with said diode, said series diode and resistor coupling said weighting signal to said differential amplifier circuit; and c. a second resistor coupled between said differential amplifier circuit and a reference potential.

Claim 14

The apparatus of claim 11 wherein said diode includes a Schottky Barrier diode.

Claim 15

An AGC weighted diversity combiner circuit responsive to AGC voltages from AGC loops of a plurality of receivers as well as respective instantaneous input signal and noise voltages of the receivers for combining a plurality of diversity signals whereby the output signal to noise ratio is maximized comprising: a. a plurality of weighting circuits each responsive to a respective independent one of said AGC voltage from a respective one of said AGC loops and to respective said instantaneous input signal and noise voltages from respective said receivers for generating a plurality of respective independent weighted diversity signals, each respective weighted diversity signal being associated with a respective receiver; and b. means for summing said plurality of weighted diversity signals, said summed diversity signals being the output signal and noise voltages with maximized signal-to-noise ratio.

Claim 16

An AGC weighted diversity combiner circuit responsive to AGC voltages from AGC loops of a plurality of receivers as well as respective instantaneous input signal and noise voltages of the receivers for combining a plurality of diversity signals whereby the output signal to noise ratio is maximized comprising: a. a plurality of weighting circuits each responsive to a respective independent one of said AGC voltage from a respective one of said AGC loops and to respective said instantaneous input signal and noise voltages from respective said receivers for generating a plurality of respective independent weighted diversity signals, each respective weighted diversity signal being associated with a respective receiver; and b. means for summing said plurality of weighted diversity signals, said summed diversity signals being the output signal and noise voltages with maximized signal-to-noise ratio.

Claim 17

The apparatus of claim 13 further including a high pass filter coupled to receive said output signal and noise voltages.

Claim 18

An AGC weighted diversity combiner circuit responsive to AGC voltages from AGC loops of a plurality of receivers as well as respective instantaneous input signal and noise voltages of the receivers for combining a plurality of diversity signals whereby the output signal to noise ratio is maximized comprising: a. a plurality of weighting circuits responsive to said AGC voltages and to said respective instantaneous input signal and noise voltages from said receivers for generating a plurality of weighted diversity signals, each weighted diversity signal being associated with a respective receiver; and b. each said weighting circuit including: a differential amplifier circuit having common emitters, said differential amplifier circuit being coupled to receive said weighting signal; a common emitter circuit responsive to said input signal and noise voltages and coupled to said common emitters of said differential amplifier circuit; and means responsive to said weighting signal and coupled to said differential amplifier circuit for selecting one of said weighting circuits as a reference channel; and c. means for summing said plurality of weighted diversity signals, said summed diversity signals being the output signal and noise voltages with maximized signal-to-noise ratio.

Claim 19

An AGC weighted diversity combiner circuit responsive to AGC voltages from AGC loops of a plurality of receivers as well as respective instantaneous input signal and noise voltages of the receivers for combining a plurality of diversity signals whereby the output signal to noise ratio is maximized comprising: a. a plurality of weighting circuits responsive to said AGC voltages and to said respective instantaneous input signal and noise voltages from said receivers for generating a plurality of weighted diversity signals, each weighted diversity signal being associated with a respective receiver; and b. each said weighting circuit including: a differential amplifier circuit having common emitters, said differential amplifier circuit being coupled to receive said weighting signal; a common emitter circuit responsive to said input signal and noise voltages and coupled to said common emitters of said differential amplifier circuit; and means responsive to said weighting signal and coupled to said differential amplifier circuit for selecting one of said weighting circuits as a reference channel; and c. means for summing said plurality of weighted diversity signals, said summed diversity signals being the output signal and noise voltages with maximized signal-to-noise ratio.

Claim 20

The apparatus of claim 15 wherein said differential amplifier circuit comprises: a. a first transistor having a base, an emitter, and a collector; b. a second transistor having a base, an emitter, and a collector, said first and second transistor being substantially identical, said second transistor base being coupled to said selecting means, said second transistor emitter being coupled to said first transistor emitter, said first transistor collector being coupled to a second bias voltage, said weighted signal appearing on the collector of said second transistor; and c. a first resistor coupled between the base of said first transistor and said weighting signal; d. a second resistor coupled between the base of said first transistor and a reference voltage; e. a third resistor coupled between the collector of said first transistor and said first resistor; and f. a diode circuit for coupling said weighting signal to said first resistor.

Claim 21

The apparatus of claim 16 wherein said diode circuit includes a Schottky Barrier diode.

Claim 22

The apparatus of claim 16 wherein said common emitter circuit includes: a. a third transistor having an emitter, a collector, and a base, said third transistor collector being coupled to said first and second transistor emitters, said third transistor base being coupled to receive said input signal and noise voltages; b. a capacitor having a first and a second side, said first side being coupled to a reference voltage; and c. a fourth resistor being coupled between said third transistor emitter and said second side of said capacitor.

Claim 23

The apparatus of claim 18 wherein the values of said first (R 1 ) and second (R 2 ) resistors are given by the following relationships R.sub.1 /R.sub.2 =(K.sub.1 -2K.sub.3 /2K.sub.3) where K 3 =kT/q log e and k=Boltzman's constant T=Absolute Temperature q=electron charge e=2.71828 . . . log=logarithm to the base 10 K 1 =a constant unique to a particular receiver.

Claim 24

The apparatus of claim 15 wherein said selecting means includes a diode circuit responsive to said weighting signal.

Claim 25

The apparatus of claim 20 wherein said diode circuit includes: a. a diode; b. a first resistor in series with said diode, said series diode and resistor coupling said weighting signal to said differential amplifier circuit; and c. a second resistor coupled between said differential amplifier circuit and a reference potential.

Claim 26

The apparatus of claim 21 wherein said diode includes a Schottky Barrier diode.