Jsit-type field effect transistor with deep level channel doping

Claim 2

In a semiconductor device of the type which comprises: a source semiconductor region having a first conductivity type; a drain semiconductor region having said first conductivity type; a channel semiconductor region having said first conductivity type for providing a current path between said source and said drain; and a gate semiconductor region having a second conductivity type opposite to said first conductivity type and adjoining said channel to form a p-n junction with said channel; said channel being substantially pinched-off by a depletion layer developed around said p-n junction without application of an external biasing potential to said gate; said channel being rendered conductive by application of an external biasing potential to said gate to forward-bias said p-n junction, causing said depletion layer to shrink, the improvement comprising: recombination centers for minority carriers in said channel, formed in at least said channel, thereby reducing storage effect due to those minority carriers which are injected into said channel from said gate in the conductive state of said channel.

Claim 3

In a device according to claim 1, in which said recombination centers comprise a heavy metallic element doped in said channel, said heavy metallic element being one of the group consisting of gold, iron and copper.

Claim 4

In a device according to claim 2, in which said heavy metallic element is gold, wherein said first conductivity type is N-type and second conductivity type is P-type.

Claim 5

In a device according to claim 1, in which said channel, drain, gate and source semiconductor regions, respectively, are semiconductor regions formed in a single common semiconductor wafer, and in which the entire semiconductor wafer includes said recombination centers.

Claim 6

In a device according to claim 4, in which said recombination centers comprise a heavy metallic element doped in said semiconductor wafer, said heavy metallic element being one of the group consisting of gold, iron and copper.

Claim 7

In a device according to claim 4, in which said recombination centers comprise gold doped in said semiconductor wafer, and wherein said first conductivity type is N-type and said second conductivity type is P-type.

Claim 8

An integrated semiconductor device including at least one unit comprising a bipolar injector transistor and a junction field effect driver transistor, the two transistors being formed in a single common monolithic semiconductor wafer; said driver transistor comprising: a drain semiconductor region having a first conductivity type; a source semiconductor region having said first conductivity type; a channel semiconductor region located between said source region and said drain region and having said first conductivity type; and a gate semiconductor region having a second conductivity type opposite to said first conductivity type, said gate region being provided adjacent to said channel region to make, jointly with said channel region, a p-n junction defining a boundary of said channel region and providing a depletion layer growing from said gate region into said channel region; said depletion layer growing enough to substantially pinch-off said channel region with said p-n junction being other than forward-biased; said injector transistor comprising: an emitter semiconductor region having said second conductivity type and provided adjacent to, but separated from, said gate region of said driver transistor; a collector semiconductor region having said second conductivity type and merged into said gate region of said driver transistor; and a base semiconductor region having said first conductivity type and sandwiched between said emitter region and said gate region; said emitter region being responsive to a biasing potential applied thereto to inject charge carriers through said base region into said gate region so as to forward-bias said p-n junction, thereby causing said depletion layer to shrink and rendering said channel region conductive; and means for reducing storage effect due to the minority carriers which are injected into said channel region from said gate region in the conductive state of said channel region, said means comprising recombination centers for minority carriers formed in said channel region.

Claim 9

An integrated semiconductor device including at least one unit comprising a bipolar injector transistor and a junction field effect driver transistor, the two transistors being formed in a single common monolithic semiconductor wafer; said driver transistor comprising: a drain semiconductor region having a first conductivity type; a source semiconductor region having said first conductivity type; a channel semiconductor region located between said source region and said drain region and having said first conductivity type; and a gate semiconductor region having a second conductivity type opposite to said first conductivity type, said gate region being provided adjacent to said channel region to make, jointly with said channel region, a p-n junction defining a boundary of said channel region and providing a depletion layer growing from said gate region into said channel region; said depletion layer growing enough to substantially pinch-off said channel region with said p-n junction being other than forward-biased; said injector transistor comprising: an emitter semiconductor region having said second conductivity type and provided adjacent to, but separated from, said gate region of said driver transistor; a collector semiconductor region having said second conductivity type and merged into said gate region of said driver transistor; and a base semiconductor region having said first conductivity type and sandwiched between said emitter region and said gate region; said emitter region being responsive to a biasing potential applied thereto to inject charge carriers through said base region into said gate region so as to forward-bias said p-n junction, thereby causing said depletion layer to shrink and rendering said channel region conductive; and means for reducing storage effect due to the minority carriers which are injected into said channel region from said gate region in the conductive state of said channel region, said means comprising recombination centers for minority carriers formed in said channel region.

Claim 10

An integrated semiconductor device according to claim 7 in which said recombination centers in said channel region comprise a heavy metallic element doped in said channel region, said heavy metallic element being one of the group consisting of gold, iron and copper.

Claim 11

An integrated semiconductor device according to claim 8 in which said heavy metallic element is gold and wherein said first conductivity type is N-type, and said second conductivity type is P-type.

Claim 12

An integrated semiconductor device according to claim 8 in which said heavy metallic element is doped in the entire region of said wafer.

Claim 13

In a semiconductor device of the type including source, drain, gate and channel semiconductor regions, said source, drain and channel regions being of a first conductivity type and said gate region being of a second conductivity type opposite to said first conductivity type, said source, drain and gate regions being relatively disposed to define a controlled current path between said source and drain regions through said channel region, said gate and channel regions forming a p-n junction therebetween, said p-n junction generating a depletion layer extending across said channel to at least nearly pinch-off said current path through said channel region in the absence of an externally applied forward-bias across said junction, the improvement wherein: said device includes means for reducing storage effect due to minority carriers injected into said channel region from said gate region in the conductive state of said channel region, said means comprising recombination centers for minority carriers formed in said channel.

Claim 14

In a semiconductor device of the type including source, drain, gate and channel semiconductor regions, said source, drain and channel regions being of a first conductivity type and said gate region being of a second conductivity type opposite to said first conductivity type, said source, drain and gate regions being relatively disposed to define a controlled current path between said source and drain regions through said channel region, said gate and channel regions forming a p-n junction therebetween, said p-n junction generating a depletion layer extending across said channel to at least nearly pinch-off said current path through said channel region in the absence of an externally applied forward-bias across said junction, the improvement wherein: said device includes means for reducing storage effect due to minority carriers injected into said channel region from said gate region in the conductive state of said channel region, said means comprising recombination centers for minority carriers formed in said channel.

Claim 15

In a device according to claim 11, in which said recombination centers comprise a heavy metallic element doped in said channel, said heavy metallic element being one of the group consisting of gold, iron and copper.

Claim 16

In a device according to claim 12, in which said heavy metallic element is gold, wherein said first conductivity type is N-type and second conductivity type is P-type.

Claim 17

In a device according to claim 11, in which said channel, drain, gate and source semiconductor regions, respectively, are semiconductor regions formed in a single common semiconductor wafer, and in which the entire semiconductor wafer includes said recombination centers.

Claim 18

In a device according to claim 14, in which said recombination centers comprise gold doped in said semiconductor wafer, and wherein said first conductivity type is N-type and said second conductivity type is P-type.

Claim 19

In a semiconductor device of the type including source, drain, gate and channel semiconductor regions, said source, drain and channel regions being of a first conductivity type opposite to said first conductivity type, said source, drain and gate regions being relatively disposed to define a controlled current path between said source and drain regions through said channel region, said gate and channel region forming a p-n junction therebetween, said p-n junction generating a depletion layer extending across said channel to at least nearly pinch-off said current path through said channel region in the absence of an externally applied forward-bias across said junction, a method for reducing storage effect due to minority carriers injected into said channel, comprising the step of forming recombination centers for minority carriers in at least said channel semiconductor region.

Claim 20

In a semiconductor device of the type including source, drain, gate and channel semiconductor regions, said source, drain and channel regions being of a first conductivity type opposite to said first conductivity type, said source, drain and gate regions being relatively disposed to define a controlled current path between said source and drain regions through said channel region, said gate and channel region forming a p-n junction therebetween, said p-n junction generating a depletion layer extending across said channel to at least nearly pinch-off said current path through said channel region in the absence of an externally applied forward-bias across said junction, a method for reducing storage effect due to minority carriers injected into said channel, comprising the step of forming recombination centers for minority carriers in at least said channel semiconductor region.

Claim 21

The method of claim 16 wherein said forming step comprises doping said channel region with a heavy metallic element taken from the group consisting of gold, iron and copper.