US4205274A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power amplifier circuit
Assignee: Sony Corp
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Filing: 1979-01-29
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Granted: 1980-05-27
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Expires: 1999-01-29
Abstract
Abstract A power amplifier circuit is mainly composed of an amplifier including an input transistor, a driving transistor and a power amplifying transistor. This power amplifying transistor is connected at its output end to an output transformer the secondary winding of which is connected to a first adjusting means for adjusting an output impedance of the power amplifying transistor. A second adjusting means, which is interlocked with the first adjusting means, is provided on the current path of the driving transistor to adjust the value of an emitter resistance of the driving transistor, and the biasing voltage of the power amplifying transistor is obtained from the current path of the driving transistor, thus the power consumption of this circuit being reduced by the adjustment of the first and second adjusting means.
Inventors
- 👤 Keizo Tsukada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:41
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/02; H03F1/0205; H03F1/0211; H03F1/0244; H03F3/00; H03F3/20; H03F3/21; H03F3/26; H03G; H03G3/00; H03G3/02; H03G3/04
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
126 words
A power amplifier circuit comprising: (a) an amplifying circuit including an input transistor, a driving transistor having a resistor in its emitter circuit, and a power amplifying transistor, each of said transistors having input, output and common electrodes; (b) a loudspeaker; (c) an output transformer provided between said power amplifying transistor and said loudspeaker; (d) a first adjusting means connected to said output transformer for adjusting the output impedance of said output transformer; (e) a second adjusting means for adjusting the value of said emitter resistor of said driving transistor, said second adjusting means being interlocked with said first adjusting means; and (f) a biasing means connected to said emitter resistor of said driving transistor and for producing a biasing voltage for said power amplifying transistor.
Claim 2
Dependent Claim
126 words
A power amplifier circuit comprising: (a) an amplifying circuit including an input transistor, a driving transistor having a resistor in its emitter circuit, and a power amplifying transistor, each of said transistors having input, output and common electrodes; (b) a loudspeaker; (c) an output transformer provided between said power amplifying transistor and said loudspeaker; (d) a first adjusting means connected to said output transformer for adjusting the output impedance of said output transformer; (e) a second adjusting means for adjusting the value of said emitter resistor of said driving transistor, said second adjusting means being interlocked with said first adjusting means; and (f) a biasing means connected to said emitter resistor of said driving transistor and for producing a biasing voltage for said power amplifying transistor.
Claim 3
Dependent Claim
13 words
A power amplifier circuit according to claim 1, which is a battery-driven circuit.
Claim 4
Dependent Claim
24 words
A power amplifier circuit according to claim 1, in which said first adjusting means is provided at the secondary side of said output transformer.
Claim 5
Dependent Claim
26 words
A power amplifier circuit according to claim 1, in which said first adjusting means and said second adjusting means are each formed of a change-over switch.
Claim 6
Dependent Claim
41 words
A power amplifier circuit according to claim 4, which further includes a tuning indicator means and a switching means for changing-over ON and OFF of said tuning indicator means, said switching means being interlocked with said first and second adjusting means.
Claim 7
Dependent Claim
28 words
A power amplifier circuit according to claim 1, which further includes a tone adjusting means, said tone adjusting means being interlocked with said first and second adjusting means.
Claim 8
Dependent Claim
19 words
A power amplifier circuit according to claim 1, in which said power amplifying transistor is formed in push-pull configuration.
Claim 9
Dependent Claim
157 words
A power amplifier circuit comprising: (a) an input stage; (b) an amplifying stage connected to said input stage and including input, driving and output transistors each having base, collector and emitter electrodes; (c) a battery source for supplying a DC voltage to said transistors; (d) a load coupled to said output transistor; (e) an output transformer connected between said output transistor and said load; (f) a first adjusting means connected to said output transformer and for varying an output impedance of said output transistor; (g) an emitter circuit connected to the emitter electrode of said driving transistor and including a resistor means; (h) a biasing means connected to said emitter circuit and for providing a biasing voltage to be supplied to the base electrode of said output transistor; and (i) a second adjusting means for varying the value of said resistor means of said emitter circuit, said second adjusting means being interlocked with said first adjusting means.
Claim 10
Dependent Claim
157 words
A power amplifier circuit comprising: (a) an input stage; (b) an amplifying stage connected to said input stage and including input, driving and output transistors each having base, collector and emitter electrodes; (c) a battery source for supplying a DC voltage to said transistors; (d) a load coupled to said output transistor; (e) an output transformer connected between said output transistor and said load; (f) a first adjusting means connected to said output transformer and for varying an output impedance of said output transistor; (g) an emitter circuit connected to the emitter electrode of said driving transistor and including a resistor means; (h) a biasing means connected to said emitter circuit and for providing a biasing voltage to be supplied to the base electrode of said output transistor; and (i) a second adjusting means for varying the value of said resistor means of said emitter circuit, said second adjusting means being interlocked with said first adjusting means.
Claim 11
Dependent Claim
64 words
A power amplifier circuit according to claim 8, in which said output transformer comprises a primary winding connected to said output transistor and a secondary winding, said secondary winding having first and second taps to be selectively connected to said load through said first adjusting means, said first tap being connected to said input transistor through a resistor to form a negative feedback loop.
Claim 12
Dependent Claim
70 words
A power amplifier circuit according to claim 8, in which said input stage includes a tone control circuit connected to said base electrode of said input transistor, said tone control circuit comprising first and second capacitors connected in parallel with each other, a third adjusting means selectively coupling said first and second capacitors to said input transistor, said third adjusting means being interlocked with said first and second adjusting means.
Claim 13
Dependent Claim
112 words
A power amplifier circuit according to claim 8, in which said input stage includes an intermediate frequency amplifier for amplifying a signal received by a radio frequency circuit, a detector for detecting an audio signal to be supplied to said input transistor, and a tuning indicator circuit connected to said intermediate frequency amplifier, said tuning indicator circuit comprising a rectifier, an active element applied with a rectified signal produced by said rectifier and an indicator means connected to said active element, wherein said indicator means is selectively applied with a DC voltage from said battery source through a switch means, said switch means being interlocked with said first and second adjusting means.
References Cited (Backward Citations)
US3492585A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-05-27 | 1983-11-26 | 1984-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-05-27 | 1987-11-26 | 1988-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-05-27 | 1991-11-26 | 1992-05-27 | $7700.00 | Window Closed / Lapsed |