Carry anticipator circuit and method

Claim 2

A carry anticipator circuit suitable for use within a data processor for reducing the time required to perform arithmetic operations, comprising: (a) first means for providing a first digital signal having a first predetermined number of bits; (b) second means for providing a second digital signal having a second predetermined number of bits, the second predetermined number being greater than the first predetermined number, the second digital signal being provided as a most significant group and a least significant group of bits, the least significant group having the first predetermined number of bits, and the most significant group of bits corresponding to a first binary value; (c) arithmetic means having first input means coupled to the first means for receiving the first digital signal and second input means coupled to the second means for receiving the least significant group of bits, the arithmetic means performing an arithmetic operation upon the bits received by the first and second input means to provide a least significant result having the first predetermined number of bits, the arithmetic means also providing a carry signal for indicating whether a carry-out resulted from the operation performed by the arithmetic means; (d) third means coupled to the second means for receiving the most significant group of bits and for providing an incremented group of bits, the incremented group of bits corresponding to a second binary value which is one larger than the first binary value; and (e) fourth means coupled to the third means for receiving the incremented group of bits and coupled to the second means for receiving the most significant group of bits, the fourth means being responsive to the carry signal for selecting either the most significant group of bits or the incremented group of bits and providing the selected bits as a most significant result.

Claim 3

A carry anticipator circuit as recited in claim 1 wherein the second predetermined number is equal to twice the first predetermined number such that the most significant group of bits has the first predetermined number of bits.

Claim 4

A carry anticipator circuit as recited in claim 1 wherein the arithmetic means includes a binary adder circuit suitable for adding two binary words to provide the least significant result, each of the binary words having the first predetermined number of bits, the binary adder circuit also being suitable for providing the carry signal as a first logic level when an addition of the two binary words generates a carry-out and as a second logic level when the addition does not generate a carry-out.

Claim 5

A carry anticipator circuit as recited in claim 3 wherein the fourth means comprises a temporary register and a digital bus, the temporary register temporarily storing the most significant group of bits, and the digital bus being coupled to the temporary register and to the third means for transmitting the selected bits.

Claim 6

A carry anticipator circuit as recited in claim 4 wherein the fourth means selects the most significant group of bits from the temporary register onto the digital bus when the carry signal is at the second logic level and selects the incremented group of bits from the third means onto the digital bus when the carry signal is at the first logic level.

Claim 7

A carry anticipator circuit as recited in claim 1 further comprising a means for generating clocking signals for effecting first and second clock cycles, the first clock cycle occurring prior to the second clock cycle, the arithmetic means and third means being operative during the first clock cycle to provide the least significant result and the incremented group of bits, respectively, and the fourth means being operative during the second clock cycle to provide the most significant result.

Claim 10

The method of claim 7 wherein the first operand includes a sign bit for indicating both positive and negative magnitudes, the modifying step including the step of selectively decrementing the most significant group of bits in a decrement circuit to form a decremented group of bits, the selection of the incrementing or decrementing steps being determined by the sign bit of the first operand.

Claim 11

The method of claim 8 wherein the step of selecting the most significant group or the modified group of bits is also a function of the sign bit of the first operand.

Claim 12

A carry anticipator circuit suitable for use within a data processor for reducing the time required to perform arithmetic operations, comprising: (a) first means for providing a first digital signal having a first predetermined number of bits, the first digital signal including a most significant bit having a first and a second logic level, the most significant bit being at the first logic level when the first digital signal is positive and being at the second logic level when the first digital signal is negative; (b) second means for providing a second digital signal having a second predetermined number of bits, the second predetermined number being greater than the first predetermined number, the second digital signal being provided as a most significant group and a least significant group of bits, the least significant group having the first predetermined number of bits, and the most significant group of bits corresponding to a first binary value; (c) arithmetic means having a first input coupled to the first means for receiving the first digital signal and a second input coupled to the second means for receiving the least significant group of bits, the arithmetic means performing an arithmetic operation upon the bits received by the first and second inputs to provide a least significant result having the first predetermined number of bits, the arithmetic means also providing a carry signal for indicating whether a carry-out resulted from the operation performed by the arithmetic means; (d) third means coupled to the second means for receiving the most significant group of bits and being responsive to the most significant bit of the first digital signal for selectively providing an incremented group of bits when the most significant bit is at the first logic level and providing a decremented group of bits when the most significant bit is at the second logic level, the incremented group of bits corresponding to a second binary value which is one larger than the first binary value and the decremented group of bits corresponding to a third binary value which is one smaller than the first binary value; and (e) fourth means coupled to the second means for receiving the most significant group of bits and coupled to the third means for receiving the incremented or decremented group of bits, the fourth means being responsive to the carry signal and responsive to the most significant bit of the first digital signal for selecting either the most significant group of bits or the incremented or decremented group of bits and providing the selected bits as a most significant result.

Claim 13

A carry anticipator circuit suitable for use within a data processor for reducing the time required to perform arithmetic operations, comprising: (a) first means for providing a first digital signal having a first predetermined number of bits, the first digital signal including a most significant bit having a first and a second logic level, the most significant bit being at the first logic level when the first digital signal is positive and being at the second logic level when the first digital signal is negative; (b) second means for providing a second digital signal having a second predetermined number of bits, the second predetermined number being greater than the first predetermined number, the second digital signal being provided as a most significant group and a least significant group of bits, the least significant group having the first predetermined number of bits, and the most significant group of bits corresponding to a first binary value; (c) arithmetic means having a first input coupled to the first means for receiving the first digital signal and a second input coupled to the second means for receiving the least significant group of bits, the arithmetic means performing an arithmetic operation upon the bits received by the first and second inputs to provide a least significant result having the first predetermined number of bits, the arithmetic means also providing a carry signal for indicating whether a carry-out resulted from the operation performed by the arithmetic means; (d) third means coupled to the second means for receiving the most significant group of bits and being responsive to the most significant bit of the first digital signal for selectively providing an incremented group of bits when the most significant bit is at the first logic level and providing a decremented group of bits when the most significant bit is at the second logic level, the incremented group of bits corresponding to a second binary value which is one larger than the first binary value and the decremented group of bits corresponding to a third binary value which is one smaller than the first binary value; and (e) fourth means coupled to the second means for receiving the most significant group of bits and coupled to the third means for receiving the incremented or decremented group of bits, the fourth means being responsive to the carry signal and responsive to the most significant bit of the first digital signal for selecting either the most significant group of bits or the incremented or decremented group of bits and providing the selected bits as a most significant result.

Claim 14

A carry anticipator circuit as recited in claim 10 further comprising a means for generating clocking signals for effecting first and second clock cycles, the first clock cycle occurring prior to the second clock cycle, the arithmetic means and third means being operative during the first clock cycle to provide the least significant result and the incremented or decremented group of bits, respectively, and the fourth means being operative during the second clock cycle to provide the most significant result.